5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_RSVD17
CFG0
CFG3
CFG4
H_RSVD18 H_RSVD65
H_RSVD64
TP_DC_TEST_BV71_BV69
TP_DC_TEST_BV68
TP_DC_TEST_BV5
TP_DC_TEST_BV3_BT3
TP_DC_TEST_BV1_BT1
TP_DC_TEST_BT71_BT69
TP_DC_TEST_BR71
TP_DC_TEST_BR1
TP_DC_TEST_E71
TP_DC_TEST_E1
TP_DC_TEST_C71_A71
TP_DC_TEST_C69_A69
TP_DC_TEST_C3
TP_DC_TEST_A68
TP_DC_TEST_A5
CFG10
CFG11
CFG13
CFG14
CFG15
CFG16
CFG17
CFG12
CFG1
CFG2
CFG0
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
H_RSVD37
H_RSVD32
H_RSVD33
H_RSVD41
CFG108
CFG118
CFG08
CFG18
CFG28
CFG38
CFG48
CFG58
CFG68
CFG78
CFG88
CFG98
Title
Size Document Number Rev
Date: Sheet
of
LA-5691P
0.1
Auburndale (4/6)
10 51Monday, July 13, 2009
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
LA-5691P
0.1
Auburndale (4/6)
10 51Monday, July 13, 2009
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
LA-5691P
0.1
Auburndale (4/6)
10 51Monday, July 13, 2009
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
PCI-Express Configuration Select
CFG0
1 : Single PEG
0 : Bifurcation enable
PCI-Express Static Lane Reversal
CFG3
1 : Normal Operation
0 : Lane Number Reversed
15->0, 14->1 ...
Display Port Presence
CFG4
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
Package Daisy Chain:
1: BR71 - pkg - BT71- board - BT69 - pkg - BV71 - board - BV69 - pkg - BV68
2: A68 - pkg - A69 - board - C69 - pkg - A71 - board - C71 - pkg - E71
3: A5 - pkg - C3
4: BR1 - pkg - BT1 - board - BV1 - pkg - BT3 - board - BV3 - pkg - BV5
1
2
3
4
*
Reserve VIA on PCB
R830
0_0402_5%~D
@
R830
0_0402_5%~D
@
12
R831
0_0402_5%~D
@
R831
0_0402_5%~D
@
12
R83
0_0402_5%~D
@ R83
0_0402_5%~D
@
1 2
T187T187
R1507
0_0402_5%~D
@
R1507
0_0402_5%~D
@
12
T185T185
R84 0_0402_5%~D@R84 0_0402_5%~D@
12
RESERVED
REV1.0
U2E
AUBURNDALE SFF_BGA1288~D
RESERVED
REV1.0
U2E
AUBURNDALE SFF_BGA1288~D
CFG[0]
AL4
CFG[1]
AM2
CFG[2]
AK1
CFG[3]
AK2
CFG[4]
AK4
CFG[5]
AJ2
CFG[6]
AT2
CFG[7]
AG7
CFG[8]
AF4
CFG[9]
AG2
CFG[10]
AH1
CFG[11]
AC2
CFG[12]
AC4
CFG[13]
AE2
CFG[14]
AD1
CFG[15]
AF8
CFG[16]
AF6
CFG[17]
AB7
RSVD34
AC69
RSVD35
AC71
RSVD38
R66
RSVD_NCTF[2]
BV6
RSVD39
R64
RSVD_NCTF[3]
BT5
RSVD_NCTF[4]
BR5
RSVD_NCTF[1]
BV8
RSVD_TP[0]
AU1
RSVD45
AV69
RSVD46
AK71
RSVD47
AN69
RSVD48
AP66
RSVD49
AH66
RSVD50
AK66
RSVD51
AR71
RSVD52
AM66
RSVD53
AK69
RSVD54
AU71
RSVD55
AT70
RSVD56
AR69
RSVD57
AU69
RSVD58
AT67
RSVD_NCTF[6]
E3
RSVD_NCTF[5]
F1
RSVD_NCTF[7]
C5
RSVD_NCTF[8]
A6
RSVD27
B9
RSVD26
A10
RSVD62
AV4
RSVD63
AU2
RSVD16
T2
RSVD15
T4
RSVD17
U1
RSVD18
V2
RSVD20
AW70
RSVD19
AV71
RSVD22
BB69
RSVD21
AY69
RSVD23
D8
RSVD24
B7
RSVD36
AA71
RSVD37
AA69
RSVD_TP[1]
AN7
RSVD_TP[2]
AP2
RSVD32
W66
RSVD33
W64
DC_TEST_BT3
BT3
DC_TEST_BT1
BT1
DC_TEST_BR71
BR71
DC_TEST_BR1
BR1
DC_TEST_E71
E71
DC_TEST_E1
E1
DC_TEST_C71
C71
DC_TEST_C69
C69
DC_TEST_C3
C3
DC_TEST_A71
A71
DC_TEST_A69
A69
DC_TEST_A68
A68
DC_TEST_A5
A5
RSVD64
BE69
RSVD65
BE71
DC_TEST_BT69
BT69
DC_TEST_BV5
BV5
DC_TEST_BV3
BV3
DC_TEST_BV1
BV1
DC_TEST_BT71
BT71
DC_TEST_BV71
BV71
DC_TEST_BV69
BV69
DC_TEST_BV68
BV68
R1108
3.01K_0402_1%~D
@
R1108
3.01K_0402_1%~D
@
12
T186T186
T56T56
R1107
3.01K_0402_1%~D
@
R1107
3.01K_0402_1%~D
@
12
R1109
3.01K_0402_1%~D
R1109
3.01K_0402_1%~D
12
R1509
0_0402_5%~D
@R1509
0_0402_5%~D
@
12
T188T188
R1508
0_0402_5%~D
@
R1508
0_0402_5%~D
@
12
R81
0_0402_5%~D
@ R81
0_0402_5%~D
@
1 2