AD7705/AD7706: 3V/5V, 16-Bit Sigma-Delta ADCs with Programmable Gain

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"AD7706是一款由Analog Devices公司生产的高性能16位sigma-delta（Σ-Δ）模数转换器（ADC），适用于需要高精度数据转换的应用。该芯片提供2个全差分输入通道（AD7705）和3个伪差分输入通道（AD7706）。其主要特点包括极低的非线性误差（0.003%），可编程增益前端，以及支持多种数字接口标准如SPI、QSPI、MICROWIRE和DSP兼容的三线串行接口。此外，它还具有Schmitt触发的SCLK输入，能够缓冲模拟输入，并能在2.7V到3.3V或4.75V到5.25V的电压范围内工作。在3V电源下最大功率耗散仅为1mW，待机电流不超过8mA。AD7706可封装在16引脚DIP、SOIC和TSSOP封装中。" AD7706的主要特性与应用： 1. **高分辨率与精度**：AD7706提供16位无缺失代码保证，这意味着在全量程范围内，转换结果的每一位都能准确表示。非线性度仅为0.003%，确保了高精度的数据转换。 2. **可编程增益前端**：增益范围从1到128，可以根据不同的信号幅度需求进行调整，扩大微弱信号的测量范围。 3. **三线串行接口**：通过SPI、QSPI、MICROWIRE或与DSP兼容的三线串行接口，可以轻松地与微控制器或处理器系统集成，简化了硬件设计。 4. **Schmitt触发SCLK输入**：这种特性保证了时钟信号的稳定性和抗噪声能力，提高了系统的可靠性。 5. **模拟输入缓冲**：AD7706具备输入缓冲功能，能保护ADC输入不受过载影响，同时增强信号的稳定性。 6. **电源适应性**：支持2.7V到3.3V及4.75V到5.25V两种电源电压范围，适合不同应用场景。 7. **低功耗与待机模式**：在3V电源下，最大功率耗散仅为1mW，待机模式下的电流消耗不超过8mA，有利于节能设计。 8. **封装选项**：16引脚的DIP、SOIC和TSSOP封装提供了设计灵活性，便于在各种尺寸和空间受限的电路板上使用。 AD7706常用于需要高精度测量的领域，如工业自动化、医疗设备、能源监测、测试与测量设备以及传感器信号处理等。结合其低功耗和高精度特性，它在便携式和远程监测系统中也有广泛应用。在实际应用中，设计者需要考虑匹配合适的外部滤波器、参考电压源和时钟源，以确保最佳性能。

AD7705/AD7706

–6–

REV. A

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 SCLK Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input

to access serial data from the AD7705/AD7706. This serial clock can be a continuous clock

with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncon-

tinuous clock with the information being transmitted to the AD7705/AD7706 in smaller

batches of data.

2 MCLK IN Master Clock signal for the device. This can be provided in the form of a crystal/resonator or

external clock. A crystal/resonator can be tied across the MCLK IN and MCLK OUT pins.

Alternatively, the MCLK IN pin can be driven with a CMOS-compatible clock and MCLK

OUT left unconnected. The part can be operated with clock frequencies in the range

500 kHz to 5 MHz.

3 MCLK OUT When the master clock for the device is a crystal/resonator, the crystal/resonator is connected

between MCLK IN and MCLK␣ OUT. If an external clock is applied to MCLK IN, MCLK

OUT provides an inverted clock signal. This clock can be used to provide a clock source for

external circuitry and is capable of driving one CMOS load. If the user does not require it,

this MCLK OUT can be turned off via the CLK DIS bit of the Clock Register. This ensures

that the part is not burning unnecessary power driving capacitive loads on MCLK OUT.

4 CS Chip Select. Active low Logic Input used to select the AD7705/AD7706. With this input

hard-wired low, the AD7705/AD7706 can operate in its three-wire interface mode with

SCLK, DIN and DOUT used to interface to the device. CS can be used to select the device

in systems with more than one device on the serial bus or as a frame synchronization signal in

communicating with the AD7705/AD7706.

5 RESET Logic Input. Active low input that resets the control logic, interface logic, calibration

coefficients, digital filter and analog modulator of the part to power-on status.

6 AIN2(+)[AIN1] AD7705: Positive input of the differential Analog Input Channel 2. AD7706: Analog Input

Channel 1.

7 AIN1(+)[AIN2] AD7705: Positive input of the differential Analog Input Channel 1. AD7706: Analog Input

Channel 2.

8 AIN1(–)[COMMON] AD7705: Negative input of the differential Analog Input Channel 1. AD7706: COMMON

Input. Analog inputs for Channels 1, 2 and 3 are referenced to this input.

9 REF IN(+) Reference Input. Positive input of the differential Reference Input to the AD7705/AD7706.

The reference input is differential with the provision that REF IN(+) must be greater than

REF IN(–). REF␣ IN(+) can lie anywhere between V

and GND.

PIN CONFIGURATIONS

TOP VIEW

(Not to Scale)

SCLK

MCLK IN

MCLK OUT

RESET

AIN2(+)

AIN1(+)

AIN1(–)

GND

DIN

DOUT

DRDY

AIN2(–)

REF IN(–)

REF IN(+)

AD7705

TOP VIEW

(Not to Scale)

SCLK

MCLK IN

MCLK OUT

RESET

AIN1

AIN2

COMMON

GND

DIN

DOUT

DRDY

AIN3

REF IN(–)

REF IN(+)

AD7706

AD7705/AD7706

–7–REV. A

Pin No. Mnemonic Function

10 REF IN(–) Reference Input. Negative input of the differential reference input to the AD7705/AD7706.

The REF␣ IN(–) can lie anywhere between V

and GND provided REF␣ IN(+) is greater

than REF␣ IN(–).

11 AIN2(–)[AIN3] AD7705: Negative input of the differential analog Input Channel 2. AD7706: Analog Input

Channel 3.

12 DRDY Logic Output. A logic low on this output indicates that a new output word is available from

the AD7705/AD7706 data register. The DRDY pin will return high upon completion of a

read operation of a full output word. If no data read has taken place between output updates,

the DRDY line will return high for 500 × t

CLK␣ IN

cycles prior to the next output update.

While DRDY is high, a read operation should neither be attempted nor in progress to avoid

reading from the data register as it is being updated. The DRDY line will return low again

when the update has taken place. DRDY is also used to indicate when the AD7705/AD7706

has completed its on-chip calibration sequence.

13 DOUT Serial Data Output with serial data being read from the output shift register on the part. This

output shift register can contain information from the setup register, communications regis-

ter, clock register or data register, depending on the register selection bits of the Communica-

tions Register.

14 DIN Serial Data Input with serial data being written to the input shift register on the part. Data

from this input shift register is transferred to the setup register, clock register or communica-

tions register, depending, on the register selection bits of the Communications Register.

15 V

Supply Voltage, +2.7 V to +5.25 V operation.

16 GND Ground reference point for the AD7705/AD7706’s internal circuitry.

OUTPUT NOISE (5 V OPERATION)

Table I shows the AD7705/AD7706 output rms noise for the selectable notch and –3␣ dB frequencies for the part, as selected by FS0

and FS1 of the Clock Register. The numbers given are for the bipolar input ranges with a V

REF

of +2.5␣ V and V

= 5 V. These

numbers are typical and are generated at an analog input voltage of 0␣ V with the part used in either buffered or unbuffered mode. Table II

meanwhile shows the output peak-to-peak noise for the selectable notch and –3 dB frequencies for the part. It is important to note that

these numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but on peak-to-peak

noise. The numbers given are for bipolar input ranges with a V

REF

of +2.5 V and for either buffered or unbuffered mode. These num-

bers are typical and are rounded to the nearest LSB. The numbers apply for the CLK DIV bit of the Clock Register set to 0.

Table I. Output RMS Noise vs. Gain and Output Update Rate @ 5 V

Filter First Typical Output RMS Noise in ␮V

Notch and O/P –3␣ dB Gain of Gain of Gain of Gain of Gain of Gain of Gain of Gain of

Data Rate Frequency 1248163264128

MCLK IN = 2.4576 MHz

50␣ Hz 13.1␣ Hz 4.1 2.1 1.2 0.75 0.7 0.66 0.63 0.6

60␣ Hz 15.72␣ Hz 5.1 2.5 1.4 0.8 0.75 0.7 0.67 0.62

250␣ Hz 65.5␣ Hz 110 49 31 17 8 3.6 2.3 1.7

500␣ Hz 131␣ Hz 550 285 145 70 41 22 9.1 4.7

MCLK IN = 1 MHz

20␣ Hz 5.24␣ Hz 4.1 2.1 1.2 0.75 0.7 0.66 0.63 0.6

25␣ Hz 6.55␣ Hz 5.1 2.5 1.4 0.8 0.75 0.7 0.67 0.62

100␣ Hz 26.2␣ Hz 110 49 31 17 8 3.6 2.3 1.7

200␣ Hz 52.4␣ Hz 550 285 145 70 41 22 9.1 4.7

剩余31页未读，继续阅读

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