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BCM53115M智能管理千兆以太网交换机详细规格
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更新于2024-07-16
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标题:"53115M-DS06-RDS.pdf"文档详细介绍了博通BCM53115M多端口千兆以太网交换机。这款高度集成的智能管理型交换机是基于成熟的ROBO架构设计,旨在提供经济高效的解决方案。它将高速交换系统的各种功能,如包缓冲、PHY收发器、媒体访问控制器(MAC)、地址管理、端口速率控制以及无阻塞交换结构整合在一个65纳米CMOS芯片中,确保完全符合IEEE 802.3和802.3x标准,包括MAC控制PAUSE帧。
该芯片的功能特点包括:
1. **高度集成**:作为单一设备,BCM53115M集成了多种功能,减少了外部组件的需求,简化了系统设计和部署。
2. **智能管理**:具备智能管理能力,能够支持标准的GbE(千兆以太网)连接,适用于桌面和笔记本电脑,以及高级应用如游戏机、机顶盒、网络DVD播放器和家庭影院接收器。
3. **兼容性广泛**:与业界标准的以太网、Fast Ethernet和GbE设备兼容,确保了设备之间的无缝通信。
4. **标准与扩展性**:符合IEEE 802.3和802.3x规范,支持MAC控制PAUSE帧,满足不同网络环境对带宽管理和控制的需求。
5. **高性能架构**:基于ROBO架构设计,提供高速数据传输和低延迟,适合需要高效率和稳定性的应用场景。
6. **无阻塞交换**:非阻塞交换设计确保了数据包在交换过程中的高效处理,减少延迟,提高网络性能。
7. **65纳米CMOS技术**:采用先进的制造工艺,有助于降低功耗和成本,同时保持高性能。
8. **地址管理和端口速率控制**:内置地址管理功能便于设备的自动配置和管理,而端口速率控制则能根据需要动态调整带宽分配。
通过这份数据表,用户可以全面了解BCM53115M的特点和优势,从而在设计和选择网络设备时做出明智决策。对于网络工程师、系统集成商和产品经理来说,这份文档提供了关键信息,帮助他们评估这款产品是否满足特定项目需求。
8/11/2009 HLWCH
BCM53115M Data Sheet
05/13/09
Broadcom Corporation
Page xvi Document 53115M-DS06-R
Spare Control 2 Register (Page 10h–14h: Address 38h) ....................................................................207
Auto Power-Down Register (Page 10h–14h: Address 38h) ................................................................208
LED Selector 2 Register (Page 10h–14h: Address 38h) .....................................................................209
Mode Control Register (Page 10h–14h: Address 38h)........................................................................210
Master/Slave Seed Register (Page 10h–14h: Address 3Ah) ..............................................................211
HCD Status Register (Page 10h–14h: Address 3Ah)..........................................................................212
Test Register 1 (Page 10h–14h: Address 3Ch)...................................................................................213
Expansion Registers ................................................................................................................................214
Expansion Register 00h: Receive/Transmit Packet Counter...............................................................214
Packet Counter (Copper Only) .....................................................................................................214
Expansion Register 01h: Expansion Interrupt Status ..........................................................................214
Transmit CRC Error......................................................................................................................214
Expansion Register 45h: Transmit CRC Enable .................................................................................215
Transmit CRC Checker ................................................................................................................215
PAGE 15h: Internal SerDes Port (Port 5) Register.................................................................................215
MII Control Register (Page 15h: Address 00h)....................................................................................217
MII Status Register (Page 15h: Address 02h) .....................................................................................218
Auto-Negotiation Advertisement Register (Page 15h: Address 08h) ..................................................219
Auto-Negotiation Link Partner Ability Register (Page 15h: Address 0Ah) ...........................................220
Auto-Negotiation Expansion Register (Page 15h: Address 0Ch) ........................................................221
Extended Status Register (Page 15h: Address 1Eh) ..........................................................................221
SerDes/SGMII Control 1 Register (Page 15h: Address 20h, Block0)..................................................222
SerDes/SGMII Control 2 Register (Page 15h: Address 22h, Block0)..................................................223
SerDes/SGMII Control 3 Register (Page15h: Address 24h, Block0)...................................................225
SerDes/SGMII Status 1 Register (Page 15h: Address 28h, Block0) ...................................................227
SerDes/SGMII Status 2 Register (Page15h: Address 2Ah, Block0)....................................................228
SerDes/SGMII Status 3 Register (Page 15h: Address 2Ch, Block0) ..................................................228
100FX Enabling Control Register (Page 15h: Address 20h, Block2) ..................................................230
100FX Extended Packet Size Register (Page 15h: Address 22h, Block2)..........................................231
100FX Control Register (Page 15h: Address 24h, Block2) .................................................................231
100FX Link Status Register (Page 15h: Address 26h, Block2) ...........................................................232
Analog TX1 Register (Page 15h: Address 20h, Block3)...................................................................... 233
Analog TX2 Register (Page 15h: Address 22h, Block3)...................................................................... 234
Analog TXAMP Register (Page 15h: Address 24h, Block3)................................................................234
Analog RX1 Register (Page 15h: Address 26h, Block3) .....................................................................234
8/11/2009 HLWCH
Data Sheet BCM53115M
05/13/09
Broadcom Corporation
Document 53115M-DS06-R Page xvii
Analog RX2 Register (Page 15h: Address 28h, Block3)..................................................................... 235
Analog PLL Register (Page 15h: Address 30h, Block3) ..................................................................... 235
Block Address Number (Page 010h–017h: Address 03Eh) ................................................................ 236
Page 20h–28h: Port MIB Registers ......................................................................................................... 237
Page 30h: QoS Registers ........................................................................................................................ 241
QoS Global Control Register (Page 30h: Address 00h)...................................................................... 242
QoS IEEE 802.1p Enable Register (Page 30h: Address 04h) ............................................................ 242
QoS DiffServ Enable Register (Page 30h: Address 06h).................................................................... 243
Port N (N=0-5, 8) PCP_To_TC Register (Page 30h: Address 10h).................................................... 243
DiffServ Priority Map 0 Register (Page 30h: Address 30h)................................................................. 244
DiffServ Priority Map 1 Register (Page 30h: Address 36h)................................................................. 245
DiffServ Priority Map 2 Register (Page 30h: Address 3Ch) ................................................................ 246
DiffServ Priority Map 3 Register (Page 30h: Address 42h)................................................................. 247
TC_To_COS Mapping Register (Page 30h: Address 62h–63h) ......................................................... 248
CPU_To_COS Map Register (Page 30h: Address 64h–67h) ............................................................. 248
TX Queue Control Register (Page 30h: Address 80h)........................................................................ 249
TX Queue Weight Register (Page 30h: Address 81h) ........................................................................ 249
COS4 Service Weight Register (Page 30h: Address 85h–86h).......................................................... 250
Page 31h: Port-Based VLAN Registers.................................................................................................. 251
Port-Based VLAN Control Register (Page 31h: Address 00h)............................................................ 251
Page 32h: Trunking Registers ................................................................................................................ 252
MAC Trunking Control Register (Page 32h: Address 00h) ................................................................. 252
Trunking Group 0 Register (Page 32h: Address 10h)......................................................................... 253
Trunking Group 1 Register (Page 32h: Address 12h)......................................................................... 253
Page 34h: IEEE 802.1Q VLAN Registers ................................................................................................ 254
Global IEEE 802.1Q Register (Pages 34h: Address 00h) .................................................................. 255
Global IEEE 802.1Q VLAN Control 1 Register (Page 34h: Address 01h) .......................................... 256
Global VLAN Control 2 Register (Page 34h: Address 02h) ................................................................ 257
Global VLAN Control 3 Register (Page 34h: Address 03h) ................................................................ 257
Global VLAN Control 4 Register (Page 34h: Address 05h) ................................................................ 258
Global VLAN Control 5 Register (Page 34h: Address 06h) ................................................................ 259
VLAN Multiport Address Control Register (Page 34h: Address 0Ah–0Bh)......................................... 259
Default IEEE 802.1Q Tag Register (Page 34h: Address 10h) ............................................................ 261
Double Tagging TPID Register (Page 34h: Address 30h–31h) .......................................................... 262
ISP Port Selection Portmap Register (Page 34h: Address 32h–33h)................................................. 262
8/11/2009 HLWCH
BCM53115M Data Sheet
05/13/09
Broadcom Corporation
Page xviii Document 53115M-DS06-R
Egress VID Remarking Table Access Register (Page 34h: Address 40h–43h) ..................................262
Egress VID Remarking Table Data Register (Page 34h: Address 44h–47h) ...................................... 263
Page 36h: DOS Prevent Register ............................................................................................................264
DOS Control Register (Page 36h: Address 00h–03h)......................................................................... 264
Minimum TCP Header Size Register (Page 36h: Address 04h)..........................................................266
Maximum ICMPv4 Size Register (Page 36h: Address 08h–0Bh) .......................................................266
Maximum ICMPv6 Size Register (Page 36h: Address 0Ch–0Fh) .......................................................266
DOS Disable Learn Register (Page 36h: Address 10h) ......................................................................266
Page 40h: Jumbo Frame Control Register .............................................................................................267
Jumbo Frame Port Mask Register (Page 40h: Address 01h)..............................................................267
Standard Max Frame Size Register (Page 40h: Address 05h) ...........................................................268
Page 41h: Broadcast Storm Suppression Register...............................................................................269
Ingress Rate Control Configuration Register (Page 41h: Address 00h)..............................................269
Port Receive Rate Control Register (Page 41h: Address 10h) ...........................................................271
Port Egress Rate Control Configuration Register (Page 41h: Address 80h–91h)...............................274
IMP Port (IMP/Port 5) Egress Rate Control Configuration Register (Page 41h: Address C0h–C1h)..275
Page 42h: EAP Register...........................................................................................................................276
EAP Global Control Register (Page 42h: Address 00h) ......................................................................276
EAP Multiport Address Control Register (Page 42h: Address 01h) ....................................................277
EAP Destination IP Register 0 (Page 42h: Address 02h)....................................................................277
EAP Destination IP Register 1 (Page 42h: Address 0Ah) ...................................................................277
Port EAP Configuration Register (Page 42h: Address 20h) ................................................................278
Page 43h: MSPT Register ........................................................................................................................ 279
MSPT Control Register (Page 43h: Address 00h)...............................................................................279
MSPT Aging Control Register (Page 43h: Address 02h) ....................................................................279
MSPT Table Register (Page 43h: Address 10h) .................................................................................280
SPT Multiport Address Bypass Control Register (Page 43h: Address 50h–51h)................................281
Page 70h: MIB Snapshot Control Register.............................................................................................281
MIB Snapshot Control Register (Page 70h: Address 00h) ..................................................................282
Page 71h: Port Snapshot MIB Control Register ....................................................................................282
Page 72h: Loop Detection Register ........................................................................................................282
Loop Detection Control Register (Page 72h: Address 00h) ................................................................283
Discovery Frame Timer Control Register (Page 72h: Address 02h) ...................................................283
LED Warning Port Map Register (Page 72h: Address 03h) ................................................................283
Module ID 0 Register (Page 72h: Address 05h)..................................................................................284
8/11/2009 HLWCH
Data Sheet BCM53115M
05/13/09
Broadcom Corporation
Document 53115M-DS06-R Page xix
Module ID 1 Register (Page 72h: Address 0Bh) ................................................................................. 284
Loop Detect Source Address Register (Page 72h: Address 11h)....................................................... 284
Page 85h: WAN Interface (Port 5) External PHY MII Registers ............................................................ 284
Page 88h: IMP Port External PHY MII Registers Page Summary......................................................... 284
Page 90h: BroadSync HD Register......................................................................................................... 285
BroadSync HD Enable Control Register (Page 90h: Address 00h–01h) ............................................ 285
BroadSync HD Time Stamp Report Control Register (Page 90h: Address 02h) ................................ 286
BroadSync HD Max Packet Size Register (Page 90h: Address 04h) ................................................. 286
BroadSync HD Time Base Register (Page 90h: Address 10h–13h)................................................... 286
BroadSync HD Time Base Adjustment Register (Page 90h: Address 14h–17).................................. 286
BroadSync HD Slot Number and Tick Counter Register (Page 90h: Address 18h–1Bh) ................... 287
BroadSync HD Slot Adjustment Register (Page 90h: Address 1Ch–1Fh) .......................................... 287
BroadSync HD Class 5 Bandwidth Control Register (Page 90h: Address 30h).................................. 288
BroadSync HD Class 4 Bandwidth Control Register (Page 90h: Address 60h).................................. 288
BroadSync HD Egress Time Stamp Register (Page 90h: Address 90h) ............................................ 289
BroadSync HD Egress Time Stamp Status Register (Page 90h: Address AFh)................................. 289
BroadSync HD Link Status Register (Page 90h: Address B0h–B1h) ................................................. 289
Page 91h: Traffic Remarking Register ................................................................................................... 290
Traffic Remarking Control Register (Page 91h: Address 00h)............................................................ 290
Egress Non-BroadSync HD Packet TC to PCP Mapping Register (Page 91h: Address 10h)............ 291
Page A0h: CFP TCAM Register............................................................................................................... 292
CFP Access Register (Page A0h: Address 00h–3h)........................................................................... 293
CFP TCAM Data Register 0 (Page A0h: Address 10h–13h) .............................................................. 295
CFP TCAM Data Register 1 (Page A0h: Address 14h–17h) .............................................................. 295
CFP TCAM Data Register 2 (Page A0h: Address 18h–1Bh).............................................................. 295
CFP TCAM Data Register 3 (Page A0h: Address 1Ch–1Fh).............................................................. 295
CFP TCAM Data Register 4 (Page A0h: Address 20h–23h) .............................................................. 295
CFP TCAM Data Register 5 (Page A0h: Address 24h–27h) .............................................................. 296
CFP TCAM Data Register 6 (Page A0h: Address 28h–2Bh).............................................................. 296
CFP TCAM Data Register 7 (Page A0h: Address 2Ch–2Fh).............................................................. 296
CFP TCAM Mask Register 0 (Page A0h: Address 30h–33h) ............................................................. 296
CFP TCAM Mask Register 1 (Page A0h: Address 34h–37h) ............................................................. 296
CFP TCAM Mask Register 2 (Page A0h: Address 38h–3Bh)............................................................. 297
CFP TCAM Mask Register 3 (Page A0h: Address 3Ch–3Fh)............................................................. 297
CFP TCAM Mask Register 4 (Page A0h: Address 40h–43h) ............................................................. 297
8/11/2009 HLWCH
BCM53115M Data Sheet
05/13/09
Broadcom Corporation
Page xx Document 53115M-DS06-R
CFP TCAM Mask Register 5 (Page A0h: Address 44h–47h)..............................................................297
CFP TCAM Mask Register 6 (Page A0h: Address 48h–4Bh) .............................................................297
CFP TCAM Mask Register 7 (Page A0h: Address 4Ch–4Fh) .............................................................298
CFP Action/Policy Data 0 Register (Page A0h: Address 50h–53h) ....................................................298
CFP Action/Policy Data 1 Register (Page A0h: Address 54h–57h) ....................................................299
CFP Rate Meter Data Register 0 (Page A0h: Address 60h–63h) .......................................................300
CFP Rate Meter Data Register 1 (Page A0h: Address 64h–67h) .......................................................300
CFP Rate In-Band Statistic Data Register (Page A0h: Address 70h–73h) .........................................301
CFP Rate Out-Band Statistic Data Register (Page A0h: Address 74h–77h) ......................................301
Page A1h: CFP Configuration Register ..................................................................................................302
CFP Control Register (Page A1h: Address 00h–01h) .........................................................................305
UDF Register (Pages A1h: Address 10h–ABh)...................................................................................306
Global Registers .......................................................................................................................................307
SPI Data I/O Register (Global, Address F0h)......................................................................................307
SPI Status Register (Global, Address FEh).........................................................................................307
Page Register (Global, Address FFh) .................................................................................................307
Section 8: Electrical Characteristics ............................................................................. 308
Absolute Maximum Ratings.....................................................................................................................308
Recommended Operating Conditions ....................................................................................................308
Electrical Characteristics.........................................................................................................................309
Section 9: Timing Characteristics ................................................................................. 310
Reset and Clock Timing ...........................................................................................................................310
MII Interface Timing ..................................................................................................................................311
MII Input Timing...................................................................................................................................311
MII Output Timing ................................................................................................................................312
Reverse MII Interface Timing ...................................................................................................................313
Reverse MII Input Timing ....................................................................................................................313
Reverse MII Output Timing..................................................................................................................314
RGMII Interface Timing.............................................................................................................................315
RGMII Output Timing (Normal Mode)..................................................................................................315
RGMII Output Timing (Delayed Mode) ................................................................................................316
RGMII Input Timing (Normal Mode) ....................................................................................................317
RGMII Input Timing (Delayed Mode)...................................................................................................318
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