STM32L051超低功耗32位微控制器详细数据手册

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"STM32L051是STMicroelectronics公司生产的超低功耗32位微控制器，基于ARM Cortex-M0+内核，适用于低成本硬件开发。该芯片具有16KB到64KB的闪存、8KB SRAM、2KB EEPROM，以及ADC功能。产品处于全生产阶段，发布于2017年9月，适用于-40°C到125°C的工作温度范围。" STM32L051系列微控制器是STM32 M0系列的一员，主要特点在于其出色的低功耗性能。它能在1.65V至3.6V的电源电压范围内工作，并且在不同模式下表现出极低的功耗。例如，在待机模式下，当有两个唤醒引脚时，功耗仅为0.27μA；在停止模式下，如果有16条唤醒线，功耗为0.4μA；如果在停止模式下保持RTC和8KB RAM，功耗则为0.8μA。运行模式下的电流消耗为88μA/MHz，而从RAM唤醒只需3.5μs，从闪存唤醒只需5μs。核心处理器是32位的ARM Cortex-M0+，支持最高32MHz的时钟频率，能提供0.95DMIPS/MHz的性能。内存方面，STM32L051提供高达64KB带ECC（错误校验码）的闪存存储，8KB SRAM以及2KB带ECC的数据EEPROM。此外，还有20字节的备份寄存器，并且支持闪存的扇区保护，防止非法读写操作。在I/O接口方面，该芯片最多提供了51个快速I/O端口，其中45个是5V耐压的。复位和电源管理功能包括超安全、低功耗的BOR（欠压复位）功能，有5个可选阈值，以及低功耗的POR/PDR（上电/掉电复位）。还有可编程电压检测器（PVD），增强了系统稳定性。时钟源多样，包括1到25MHz的晶体振荡器，用于RTC的32kHz振荡器并带有校准功能，以及一个16MHz的高速内部振荡器。此外，还有多种其他外设和接口，如定时器、串行通信接口等，使其适合于各种低功耗应用，如物联网设备、传感器节点、便携式设备等。

Functional overview STM32L051x6 STM32L051x8

16/131 DocID025938 Rev 8

= 2.0 to 2.4 V

Conversion time up to 1.14

Msps

Range 1, range 2 or range 3

= 2.4 to 3.6 V

Conversion time up to 1.14

Msps

Range 1, range 2 or range 3

1. GPIO speed depends on V

voltage. Refer to Table 58: I/O AC characteristics for more information about

I/O speed.

2. CPU frequency changes from initial to final must respect "fcpu initial <4*fcpu final". It must also respect 5

μs delay between two changes. For example to switch from 4.2 MHz to 32 MHz, you can switch from 4.2

MHz to 16 MHz, wait 5 μs, then switch from 16 MHz to 32 MHz.

Table 4. CPU frequency range depending on dynamic voltage scaling

CPU frequency range Dynamic voltage scaling range

16 MHz to 32 MHz (1ws)

32 kHz to 16 MHz (0ws)

Range 1

8 MHz to 16 MHz (1ws)

32 kHz to 8 MHz (0ws)

Range 2

32 kHz to 4.2 MHz (0ws) Range 3

Table 3. Functionalities depending on the operating power supply range (continued)

Operating power supply range

(1)

Functionalities depending on the operating power

supply range

ADC operation

Dynamic voltage scaling

range

Table 5. Functionalities depending on the working mode

(from Run/active down to standby)

(1)

IPs Run/Active Sleep

Low-

power

run

Low-

power

sleep

Stop Standby

Wakeup

capability

Wakeup

capability

CPU Y -- Y -- -- --

Flash memory O O O O -- --

RAM Y Y Y Y Y --

Backup registers Y Y Y Y Y Y

EEPROM O O O O -- --

Brown-out reset

(BOR)

OOOOOOOO

DMA O O O O -- --

Programmable

Voltage Detector

(PVD)

OOOOOO-

Power-on/down

reset (POR/PDR)

YYYYYYYY

Functional overview STM32L051x6 STM32L051x8

18/131 DocID025938 Rev 8

3.2 Interconnect matrix

Several peripherals are directly interconnected. This allows autonomous communication

between peripherals, thus saving CPU resources and power consumption. In addition,

these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power

run, Low-power sleep and Stop modes.

Consumption

=1.8 to 3.6 V

(Typ)

Down to

140 µA/MHz

(from Flash

memory)

Down to

37 µA/MHz

(from Flash

memory)

Down to

8 µA

Down to

4.5 µA

0.4 µA (No

RTC) V

=1.8 V

0.28 µA (No

RTC) V

=1.8 V

0.8 µA (with

RTC) V

=1.8 V

0.65 µA (with

RTC) V

=1.8 V

0.4 µA (No

RTC) V

=3.0 V

0.29 µA (No

RTC) V

=3.0 V

1 µA (with RTC)

=3.0 V

0.85 µA (with

RTC) V

=3.0 V

1. Legend:

“Y” = Yes (enable).

“O” = Optional can be enabled/disabled by software)

“-” = Not available

2. Some peripherals with wakeup from Stop capability can request HSI to be enabled. In this case, HSI is woken up by the

peripheral, and only feeds the peripheral which requested it. HSI is automatically put off when the peripheral does not need

it anymore.

3. UART and LPUART reception is functional in Stop mode. It generates a wakeup interrupt on Start. To generate a wakeup

on address match or received frame event, the LPUART can run on LSE clock while the UART has to wake up or keep

running the HSI clock.

4. I2C address detection is functional in Stop mode. It generates a wakeup interrupt in case of address match. It will wake up

the HSI during reception.

Table 5. Functionalities depending on the working mode

(from Run/active down to standby) (continued)

(1)

IPs Run/Active Sleep

Low-

power

run

Low-

power

sleep

Stop Standby

Wakeup

capability

Wakeup

capability

Table 6. STM32L0xx peripherals interconnect matrix

Interconnect

source

Interconnect

destination

Interconnect action Run Sleep

Low-

power

run

Low-

power

sleep

Stop

COMPx

TIM2,TIM21,

TIM22

Timer input channel,

trigger from analog

signals comparison

YY Y Y -

LPTIM

Timer input channel,

trigger from analog

signals comparison

YY Y Y Y

TIMx TIMx

Timer triggered by other

timer

YY Y Y -

Functional overview STM32L051x6 STM32L051x8

20/131 DocID025938 Rev 8

Nested vectored interrupt controller (NVIC)

The ultra-low-power STM32L051x6/8 embed a nested vectored interrupt controller able to

handle up to 32 maskable interrupt channels and 4 priority levels.

The Cortex-M0+ processor closely integrates a configurable Nested Vectored Interrupt

Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC:

• includes a Non-Maskable Interrupt (NMI)

• provides zero jitter interrupt option

• provides four interrupt priority levels

The tight integration of the processor core and NVIC provides fast execution of Interrupt

Service Routines (ISRs), dramatically reducing the interrupt latency. This is achieved

through the hardware stacking of registers, and the ability to abandon and restart load-

multiple and store-multiple operations. Interrupt handlers do not require any assembler

wrapper code, removing any code overhead from the ISRs. Tail-chaining optimization also

significantly reduces the overhead when switching from one ISR to another.

To optimize low-power designs, the NVIC integrates with the sleep modes, that include a

deep sleep function that enables the entire device to enter rapidly stop or standby mode.

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

3.4 Reset and supply management

3.4.1 Power supply schemes

• V

= 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided

externally through V

pins.

• V

SSA

, V

DDA

= 1.65 to 3.6 V: external analog power supplies for ADC reset blocks, RCs

and PLL. V

DDA

and V

SSA

must be connected to V

and V

, respectively.

3.4.2 Power supply supervisor

The devices have an integrated ZEROPOWER power-on reset (POR)/power-down reset

(PDR) that can be coupled with a brownout reset (BOR) circuitry.

Two versions are available:

• The version with BOR activated at power-on operates between 1.8 V and 3.6 V.

• The other version without BOR operates between 1.65 V and 3.6 V.

After the V

threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or

not at power-on), the option byte loading process starts, either to confirm or modify default

thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes

1.65 V (whatever the version, BOR active or not, at power-on).

When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever

the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the

power ramp-up should guarantee that 1.65 V is reached on V

at least 1 ms after it exits

the POR area.

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To

reduce the power consumption in Stop mode, it is possible to automatically switch off the

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