Xilinx UltraFast嵌入式设计方法与指南

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"Xilinx UG1046-ultrafast嵌入式设计方法指南" 《Xilinx UG1046-ultrafast嵌入式设计方法指南》是Xilinx公司发布的一份详细文档，旨在帮助工程师高效地进行嵌入式系统设计。这份指南自2014年10月8日首次发布以来，经过多次修订，最新版本为2.1，发布于2015年4月22日。文档的更新主要涉及添加新的章节、更新信息以及删除过时的内容，以确保提供最前沿的设计方法和技术。该指南的核心内容包括以下几个方面： 1. **嵌入式设计方法检查列表**：在第1章中，提供了嵌入式设计过程的关键步骤和注意事项的检查列表，帮助设计师确保在设计过程中遵循最佳实践，从而提高设计效率和质量。 2. **访问文档和培训**：在第2章中，详细介绍了如何获取Xilinx的相关文档和培训资源，这对于开发者来说至关重要，能够快速学习和掌握最新的设计技术和工具。 3. **系统级考虑**：在第2章中，深入探讨了系统级设计的各种关键因素： - **性能**：强调了如何优化设计以实现最佳性能，包括硬件和软件层面的优化策略。 - **功耗管理**：讨论了如何降低系统的能耗，这对于便携式和电池供电设备尤为重要。 - **时钟和复位**：详细介绍了时钟树的设计和复位管理，这些是确保系统正确运行的基础。 - **中断**：阐述了如何有效地处理中断，以实现高效的任务调度和实时响应。 - **嵌入式设备安全**：涵盖了保护设备免受攻击和数据泄露的安全措施。 - **性能分析和分区**：讨论了如何通过性能分析来确定系统组件的最佳划分，以实现资源的最佳利用。 4. **SDSoC环境**：在第8章新增的内容中，详细介绍了使用Software Defined System on Chip (SDSoC)环境进行软硬件协同设计的方法，这是Xilinx提供的一个强大的工具，用于加速基于Zynq SoC的嵌入式开发。 5. **相关设计中心**：在文档末尾，还提到了相关的设计中心，这些资源中心提供了更多关于特定设计主题的信息和实例，便于设计师深入学习和交流。通过《Xilinx UG1046-ultrafast嵌入式设计方法指南》，工程师可以获取到一套完整的ultrafast嵌入式设计流程，从系统级规划到具体实施细节，都有详尽的指导，有助于他们快速且高效地完成复杂的嵌入式系统设计任务。

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Chapter 2: System Level Considerations

Moving computations from software into the PL is an important benefit of the Zynq-7000

AP SoC platform. Not all software can be moved to the PL, in particular pre-compiled code,

complex library routines, and OS services. If it is possible to move software components to

PL, performance metrics such as the full application runtime should consider the trade-off

between data movement costs and acceleration benefits. This cost and benefit analysis can

be done using software profiling tools to determine potential speedups according to

Amdahl's law:

In the equation above, S is the overall performance improvement and α is the percentage of

the algorithm that can be sped up with hardware acceleration. Therefore 1-α is the

percentage of the algorithm that cannot be improved. The variable p is the speedup due to

acceleration. For example, to accelerate a computational algorithm implemented entirely in

software, you can use profiling tools such as TCF profiler to help identify the particular

function that is frequently used. The percentage of time with which this function is used

corresponds to a high α number. The function can then be sped up by implementing it in

hardware. The speed up of the function maps to p. Dividing a frequently used function by a

large multiplier will result in the most improvement in performance in the computation of

the algorithm due to hardware acceleration.

The speed up of a particular function has two components: the transfer of data to and from

the acceleration block and the actual computation performed by the accelerator. When a

DMA is used to perform the data transfer, the overhead for setting up and managing the

DMA must be taken into account when measuring the multiplier factor, p. If the overhead is

large, it can bound the value of p and may result in a low p factor, and therefore low

improvement in performance. For more information, refer to

Profiling and Partitioning,

page 51.

High-level synthesis provides an excellent way of moving software components to PL for

exploring acceleration options. If candidate software is not a good fit for high-level

synthesis, Xilinx also provides a rich library of programmable logic IP with corresponding

drivers which can replace functions implemented in software to improve overall system

performance.

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Chapter 2: System Level Considerations

System Monitoring

A rich tool ecosystem exists for monitoring the ARM processors. In a Zynq device, full

system-level performance monitoring also uses blocks available in the PS and PL. These are:

• SCU Global Timer (PS). The SCU global timer can be used to timestamp system events

in a single clock domain. Alternatively, operating systems often provide high accuracy

timers for software event tracing, such as Linux clock_nanosleep.

• ARM Performance Monitoring Units (PS). Each ARM core has a performance

monitoring unit (PMU) that is used to count micro-architectural events. These counters

can be accessed directly by software, through operating system utilities, or with chip

debuggers such as Linux Perf or ARM Streamline. The counters are viewable in the

Performance View of SDK 2014.2. See the Performance Monitoring Unit section in the

ARM Cortex-A9 Technical Reference Manual [Ref 75] for more information.

• L2 Cache Event Counters (PS). The L2 cache has event counters that can be accessed

to measure cache performance. The counters are viewable in the Performance Counters

View of SDK. See the Zynq-7000 All Programmable SoC Technical Reference Manual

(UG585) [Ref 4] for more information.

• GigE Controller (PS). The gigabit Ethernet controller has statistical counters to track

bytes received and transmitted on its interface. See the Zynq-7000 All Programmable

SoC Technical Reference Manual (UG585) [Ref 4] for more information.

• AXI Performance Monitor (PL). This core can be added in PL to monitor AXI

performance metrics such as throughput and latency. Trace functions enable

time-stamped AXI traces, such as time-stamped start and end of AXI transactions to

observe per-transaction latency. See the AXI Performance Monitor web page [Ref 43]

for more information.

• AXI Timer (PL). This core can be added in PL to provide a free-running timer in PL. This

timer is useful for time-stamping events in PL clock domains. See the AXI

Timer/Counter web page [Ref 44] for more information.

• AXI Traffic Generator (PL). This core can generate a variety of traffic patterns to the

PS interfaces. When used with an AXI performance monitor, the traffic generator can

help provide early system-level performance estimates. The core can be used to

estimate data-movement costs and validate design partition choices. For more

information, refer to the LogiCORE™ AXI Traffic Generator web page [Ref 45].

These monitor blocks provide visibility into the full system performance behavior. Event

counters and PL monitoring blocks can be customized for specific design performance

goals or used to get a high-level view of system performance. Early use of built-in

performance monitoring allows performance feedback throughout the design cycle,

resulting in data-driven system architecture decisions.

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UG1046 (v2.1) April 22, 2015 www.xilinx.com

Chapter 2: System Level Considerations

There are different ways of exercising or acquiring monitoring data from the various blocks.

Most peripherals come with an example application packaged with the corresponding

bare-metal driver shipped with Xilinx SDK. A list of available Linux drivers is provided in the

Xilinx Linux Drivers wiki page

[Ref 50].

Xilinx SDK provides built-in System Performance Modeling and Analysis functionality.

Performance monitors gather data from the system, either live data or data created by

traffic generators which are used to model real world transactions. This data is displayed

using the Xilinx SDK visualization tools with statistics for number of transactions,

bandwidth, and latency from an APM (profile mode) connected to the HP and ACP ports.

For more information, refer to

Xilinx SDK System Debugger, page 53.

Power Consumption

The power consumption of Zynq-7000 AP SoCs is an important consideration for system

architects and board designers. Power consumption is a critical concern for most

applications, and some applications specify maximum power per card or per system. Thus,

designers must consider power consumption early in the design process, often starting with

device selection.

Reducing SoC power consumption can improve board design by lowering supply-rail

power, simplifying power supply design and thermal management, and easing the

requirements on the power distribution planes. Low power also contributes to longer

battery life and higher reliability, because cooler-running systems last longer.

Reducing system power consumption requires a comprehensive and focused approach to

achieve optimal results. This section covers several aspects of Zynq-7000 AP SoC power

consumption, including PS and PL architecture and features, the power components

associated with PL, and the process technology. It also covers power dissipation, and

traditional methods of estimating and measuring power.

Power Challenges

According to Moore's Law, transistor size decreases with each process technology

generation. As size decreases the amount of current each transistor leaks increases, causing

an increase in static power consumption, which is the amount of current the device draws

when not switching. Increasing SoC performance requires higher-frequency clocks,

resulting in increased dynamic power consumption. Thus, static power is driven by

transistor leakage current and dynamic power is driven by the transistor switching

frequency. Compounding the problem, decreasing transistor sizes allow more transistors to

be packed on FPGAs with each product generation. More transistors results in more leakage

current and more transistors switching at higher clock frequencies on each FPGA device.

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