透明电极下全耗尽SOI基LPIN PD的光照与暗电流特性仿真研究

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本文主要探讨了一种新型的硅基光电器件——全耗尽型硅（Silicon-On-Insulator, SOI）薄膜上制作的透明电极栅控横向PIN光电二极管（Lateral PIN Photodiode with Transparent Electrode, LPIN PD-GTE）。这种设计旨在通过采用氧化铟锡（Indium Tin Oxide, ITO）作为透明电极来减少光吸收，从而提高光探测效率。在器件结构中，薄硅层在施加门电压时实现全耗尽，这有助于降低暗电流，同时增强光生电流与暗电流的比例，即光/暗电流比。研究团队，来自湖南大学物理与微电子科学学院的谢海情、曾云、曾健平和王太宏，对LPIN PD-GTE的物理模型进行了深入分析，并利用ATLAS软件进行了数值模拟。他们重点关注了在不同条件下（暗电流状态下以及570纳米光照射下的光电特性）的电流-电压特性，通过调整活性通道长度（从2到12微米），寻找最大光/暗电流比的最佳工作点。结果显示，随着活性通道长度的变化，光电二极管的性能得到了优化。当通道长度适当时，LPIN PD-GTE能够在保持低暗电流的同时，显著提升响应于光照的光电效应，这对于光通信、光探测等应用具有重要意义。通过这项研究，设计者们不仅提高了硅基光电二极管的性能，还展示了透明电极在减小光学损失和优化器件性能方面的作用，为未来的高性能光电器件设计提供了有价值的技术参考。

J. Cent. South Univ. Technol. (2011) 18: 744−748

DOI: 10.1007/s11771−011−0757−8

Analysis and simulation of lateral PIN photodiode gated by

transparent electrode fabricated on fully-depleted SOI film

XIE Hai-qing(谢海情), ZENG Yun(曾云), ZENG Jian-ping(曾健平), WANG Tai-hong(王太宏)

School of Physics and Microelectronics Science, Hunan University, Changsha 410082, China

Abstract: A novel device, lateral PIN photodiode gated by transparent electrode (LPIN PD-GTE) fabricated on fully-depleted SOI

film was proposed. ITO film was adopted in the device as gate electrode to reduce the light absorption. Thin Si film was fully

depleted under gate voltage to achieve low dark current and high photo-to-dark current ratio. The model of gate voltage was obtained

and the numerical simulations were presented by ATLAS. Current−voltage characteristics of LPIN PD-GTE obtained in dark (dark

current) and under 570 nm illumination (photo current) were studied to achieve the greatest photo-to-dark current ratio for active

channel length from 2 to 12 µm. The results show that the photo-to-dark current ratio is 2.0×10

, with dark current of around

5×10

−4

pA under V

=0.6 V, P

=5 mW/cm

, for a total area of 10 µm×10 µm in fully depleted SOI technology. Thus, the LPIN

PD-GTE can be suitable for high-grade photoelectric systems such as blue DVD.

Key words: lateral PIN photodiode; transparent electrode; physical model; photo-to-dark current ratio; silicon-on-insulator

1 Introduction

Nowadays, short distance optical communications

and optical storage (OS) systems such as blue DVD

require fast (gigahertz to tens of gigahertz bandwidth)

and responsive photodetectors with high photo-to-dark

current ratio increasingly [1−2]. Bulk silicon detectors,

however, hardly cope with these specifications, mainly in

regards to bandwidth, and nonintegrated detectors are

usually used due to high dark currents of photodiode and

low sensitivity of MOS structure (due to only one kind of

carrier and light-absorption of gate) in CMOS process

less than 0.25 µm [3−6]. The ultimate performances of

optical receiver circuits are limited because of high

bonding capacitor, cost and area, which is a limitation for

the employment in local-area networks, inter-chip/

intra-chip interconnects, and Ethernet [7−8].

Lateral PIN photodiode on SOI has been the focus

for extensive research over the past decade due to its

high responsivity and quantum efficiency [9−10].

However, high reverse bias needs to be used in this PIN

photodiode to achieve a low capacitance and high

sensitivity. In addition, it is not propitious to integration

for the small input resistance [11]. In the modern

microelectronic integration industry, MOS is the

fundamental ingredient since it has large input resistance,

low noise and wide spectrum range [12−13].

In order to achieve low dark current and high photo

current under low reverse voltage, lateral PIN

photodiode gated by transparent electrode (LPIN

PD-GTE) based on partially depleted (PD) SOI film

compatible with CMOS process was proposed recently

[14]. The structure of LPIN PD-GTE is very similar to

traditional MOS structure, but only ITO is applied as

gate to reduce the light absorption. In the previous work,

a physical model was presented based on standard

semiconductor equations under partial depletion. The

numerical calculation indicated that LPIN PD-GTE has

high sensitivity and signal to noise ratio (SNR). In this

work, the characteristics of LPIN PD-GTE fabricated on

FD SOI substrate are focused on.

2 Device structure

Thin film SOI LPIN PD-GTE was realized in the

FD SOI CMOS technology with the parameters shown in

Fig.1. The thickness of thin Si film, d

, is equal to

200 nm; the thickness of the front oxide, d

FOX

, is equal to

20 nm; the thickness of the buried oxide (BOX), d

BOX

, is

equal to 380 nm; the thickness of substrate, d

sub

, is equal

to 500 nm. The length of N

and P

zones, L

, is equal

to 1 μm and different L values, the length of the channel

typically corresponding to a P

−

-doping of 10

−3

, of 2,

4, 6, 8, 10 and 12 μm are selected.

The absorption in ITO film is the main loss of

Foundation item: Project(61040061) supported by the National Natural Science Foundation of China; Project supported by Hunan Provincial Innovation

Foundation for Postgraduate Students, China

Received date: 2010−01−31; Accepted date: 2011−01−05

Corresponding author: ZENG Yun, Professor; Tel: +86−731−88822332; E-mail: zengyun@hnu.cn

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