PCI Express单根I/O虚拟化与共享技术规范1.1版

SR-IOV

虚拟化

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"Single Root I/O Virtualization and Sharing 1.1 规范是一个由PCI-SIG发布的关于PCI Express（PCIe）I/O虚拟化和共享技术的详细文档。该规范专注于单根拓扑，即支持虚拟化技术的单一计算机系统。此规范于2010年1月20日发布，对应PCI Express Base Specification的Revision 1.x版本。文档类型为会员专享的规范，并提供了下载链接。" 《单根I/O虚拟化与共享规范》(Revision 1.1)是PCI-SIG组织发布的一项重要技术标准，旨在定义如何在基于PCI Express的系统中实现高效的I/O虚拟化。该规范的核心目标是提高I/O设备在虚拟化环境中的性能和效率，减少资源的冗余和浪费，同时简化管理和配置。 1. **SR-IOV概述** 单根I/O虚拟化（Single Root I/O Virtualization, SR-IOV）是一种技术，它允许物理PCIe设备（如网卡或显卡）被虚拟化为多个独立的逻辑功能（Function），每个功能都可以被一个单独的虚拟机（VM）直接访问，而无需通过传统的I/O虚拟化层。这样可以降低软件模拟带来的开销，提升虚拟机的I/O性能。 2. **拓扑结构** 在SR-IOV中，单个物理设备（Physical Function, PF）被虚拟化为多个虚拟功能（Virtual Functions, VF）。PF保留了对设备的控制和管理功能，而VF则作为数据传输的简单接口，每个VF都能被分配到不同的虚拟机，从而实现I/O资源的高效共享。 3. **功能分配与通信** PF和VF之间的通信通过PCI Express总线进行，VF之间的通信也通过同一总线完成，这降低了延迟并提高了性能。每个VF可以独立地配置、管理和驱动，如同它们是独立的物理设备一样。 4. **错误修正与更新** Revision 1.1是对1.0版本的更新，修复了已知错误，并反映了PCI Express Base Specification Revision 2.1中的相关变更，确保与最新标准的兼容性。 5. **责任声明** PCI-SIG明确表示不提供任何保证，也不承担因使用此文档及其包含的信息可能产生的任何错误的责任。用户需要自行联系PCI-SIG获取最新的规范修订版。 6. **联系信息** 对于文档的问题或PCI-SIG会员服务，可以通过指定的电子邮件地址、电话或传真联系。技术支持邮箱为techsupp@pcisig.com，会员服务邮箱为administration@pcisig.com。 SR-IOV技术的引入，显著提升了数据中心和云计算环境中的I/O性能，特别是在高并发、低延迟的应用场景中，如大规模网络和存储操作。它减少了虚拟化环境中I/O设备的复杂性和成本，是现代数据中心架构的重要组成部分。

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SINGLE ROOT I/O VIRTUALIZATION AND SHARING SPECIFICATION, REV. 1.10

Processor

Memory

Switch

Root

Port

(RP)

Root

Port

(RP)

PCIe Device

Root Complex (RC)

Virtualization Intermediary

SI SI SI SI SI SI

ATC

PF 0

VF 0,1 VF 0,n

SR-PCIM

Translation

Agent (TA)

Address Translation and

Protection Table (ATPT)

PCIe Device

ATC

PF 0

VF 0,1 VF 0,n

PCIe Device

ATC

PF 0

VF 0,1 VF 0,n

A-0624A

Figure 1-3: Generic Platform Configuration with SR-IOV and IOV Enablers

The SR-IOV generic platform configuration is composed of the following additional functional

elements:

 Single Root PCI Manager (SR-PCIM) – Software responsible for the configuration of the SR-

IOV capability, management of Physical Functions and Virtual Functions, and processing of

associated error events and overall device controls such as power management and hot-plug

services.

 Optional Translation Agent (TA) – A TA is hardware or a combination of hardware and

software responsible for translating an address within a PCIe transaction into the associated 10

platform physical address. A TA may contain an Address Translation Cache (ATC) to accelerate

translation table access. A TA may also support the PCI-SIG Address Translation Services

Specification which enables a PCIe Function to obtain address translations a priori to DMA access

to the associated memory. See the associated specification for more details on ATS benefits and

operation.

SINGLE ROOT I/O VIRTUALIZATION AND SHARING SPECIFICATION, REV. 1.10

 Optional Address Translation and Protection Table (ATPT) – An ATPT contains the set of

address translations accessed by a TA to process PCIe requests – DMA Read, DMA Write, or

interrupt requests. See the Address Translation Services Specification for additional details.

• In PCIe, interrupts are treated as memory write operations. Through the combination of a

Requester Identifier and the address contained within a PCIe transaction, an interrupt can be 5

routed to any target (e.g., a processor core) transparent to the associated I/O Function.

• DMA Read and Write requests are translated through a combination of the Routing ID and

the address contained within a PCIe transaction.

 Optional Address Translation Cache (ATC) – An ATC can exist in two locations within a

platform – within the TA which can be integrated within or sit above an RC – or within a PCIe

Device. Within an RC, the ATC enables accelerated translation look ups to occur. Within a

Device, the ATC is populated through ATS technology. PCIe transactions that indicate they

contain translated addresses may bypass the platform’s ATC in order to improve performance

without compromising the benefits associated with ATPT technology. See the Address

Translation Services Specification for additional details. 15

 Optional Access Control Services (ACS) – ACS defines a set of control points within a PCI

Express topology to determine whether a TLP should be routed normally, blocked, or

redirected. In a system that supports SR-IOV, ACS may be used to prevent device Functions

assigned to the VI or different SIs from communicating with one another or a peer device.

Redirection may permit a Translation Agent to translate upstream memory TLP addresses 20

before a peer-to-peer forwarding decision is made. Selective blocking may be provided by the

optional ACS P2P Egress Control. ACS is subject to interaction with ATS. See Section 3.7.2

and the PCI Express Base Specification for additional details.

 Physical Function (PF) – A PF is a PCIe Function (per the PCI Express Base Specification) that

supports the SR-IOV capability and is accessible to an SR-PCIM, a VI, or an SI. 25

 Virtual Function (VF) – A VF is a “light-weight” PCIe Function (per this specification) that is

directly accessible by an SI.

• Minimally, resources associated with the main data movement of the Function are available

to the SI. Configuration resources should be restricted to a trusted software component

such as a VI or SR-PCIM.

• A VF can be serially shared by different SI, i.e., a VF can be assigned to one SI and then

reset and assigned to another SI.

• A VF can be optionally migrated from one PF to another PF. The migration process itself is

outside the scope of this specification but is facilitated through configuration controls

defined within this specification.

 All VFs associated with a PF must be the same device type as the PF, e.g., the same network

device type or the same storage device type.

SINGLE ROOT I/O VIRTUALIZATION AND SHARING SPECIFICATION, REV. 1.10

 PF nomenclature PF

designates the PF at Function number M.

 VF nomenclature VF

M,N

designates the Nth VF associated with PF M. VFs are numbered

starting with 1 so the first VF associated with PF M is VF M,1.

 Each VF shares a number of common configuration space fields with the PF; i.e., where the

fields are applicable to all VF and controlled through a single PF. Sharing reduces the hardware 5

resource requirements to implement each VF.

• A VF uses the same configuration mechanisms and header types as a PF.

• All VFs associated with a given PF share a VF BAR set (see Section 3.3.14) and share a VF

MSE bit in the SR-IOV extended capability (see Section 3.3.3.4) that controls access to the

VF Memory space. That is, if the VF MSE bit is Clear, the memory mapped space allocated 10

for all VFs is disabled.

• The InitialVFs and TotalVFs fields (see Section 3.3.6 and Section 3.3.5) are used to discover

the maximum number of VFs that can be associated with a PF.

• If the Device does not support VF migration, TotalVFs and InitialVFs shall contain the

same value. If the Device supports VF migration, when TotalVFs is read, the PF must

return the number of VFs that can be assigned to the PF. For such a Device, when

InitialVFs is read, the PF must return the initial number of VFs assigned to the PF.

 Each Function, PF, and VF is assigned a unique Routing ID. A

The Routing ID for each PF is

constructed per default mechanism within the PCI Express Base Specification or through the

mechanism enabled via the ARI capability. The Routing ID for each VF is determined using the 20

Routing ID of its associated PF and fields in that PF’s SR-IOV Capability.

 All PCIe and SR-IOV configuration access is assumed to be through a trusted software

component such as a VI or an SR-PCIM.

 Each VF contains a non-shared set of physical resources required to deliver Function-specific

services, e.g., resources such as work queues, data buffers, etc. These resources can be directly 25

accessed by an SI without requiring VI or SR-PCIM intervention.

 One or more VF may be assigned to each SI. Assignment policies are outside the scope of this

specification.

 While this example illustrates a single ATC within the PF, the presence of any ATC is optional.

In addition, this specification does not preclude an implementation from supporting an ATC per

VF within the Device.

 Internal routing is implementation specific.

 While many potential usage models exist regarding PF operation, a common usage model is to

use the PF to bootstrap the device or platform strictly under the control of a VI. Once the SR-

IOV capability is configured enabling VF to be assigned to individual SI, the PF takes on a more

supervisory role. For example, the PF can be used to manage device-specific functionality such

as internal resource allocation to each VF, VF arbitration to shared resources such as the PCIe

Link or the Function-specific Link (e.g., a network or storage Link), etc. These policy,

management, and resource allocation operations are outside the scope of this specification.

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