GS1011M 低功耗Wi-Fi系统级芯片模块数据手册

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"GS1011M是一款低功耗无线系统级芯片Wi-Fi模块的数据手册，由GainSpan公司提供。该文档提供了关于GS1011M的技术规格、功能特性和使用注意事项。" GS1011M是GainSpan公司推出的一款集成度极高的低功耗无线SoC（System-on-Chip）解决方案，专为需要Wi-Fi功能的物联网设备设计。该模块集成了Wi-Fi通信所需的全部硬件和软件，包括射频(RF)前端、基带处理器、微控制器以及必要的存储器，旨在简化产品开发过程，降低功耗，并提高系统的整体性能。数据手册中的主要内容可能包括以下几个方面： 1. **技术规格**：详细列出GS1011M的物理尺寸、工作频率、发射功率、接收灵敏度、数据速率、功耗等关键参数，这些参数对于评估模块在实际应用中的表现至关重要。 2. **接口和连接性**：描述了GS1011M与其他系统组件（如微处理器、传感器或外部存储）的接口类型，如SPI、I2C或UART，以及如何配置和控制这些接口。 3. **无线标准兼容性**：GS1011M应符合IEEE 802.11 b/g/n标准，支持2.4GHz频段，确保其能在各种Wi-Fi网络环境中正常工作。 4. **低功耗特性**：模块可能包含了多种低功耗模式，如深度睡眠模式和智能唤醒功能，以适应电池供电或能源受限的应用场景。 5. **软件支持**：可能包括嵌入式固件、驱动程序和API库，以及对标准Wi-Fi协议的支持，如Wi-Fi Direct和Wi-Fi Alliance认证。 6. **安全特性**：可能包含WPA/WPA2等安全协议，确保无线通信的安全性。 7. **应用示例**：可能提供了GS1011M在智能家居、远程监控、工业自动化等领域的应用案例和设计指导。 8. **环境和机械规格**：耐温范围、湿度适应性以及封装材料等，确保模块在各种环境条件下稳定运行。 9. **合规性与认证**：模块应通过FCC、CE等国际和地区的无线设备认证，以满足不同市场的法规要求。 10. **警告和限制**：强调GS1011M不适用于医疗、生命支持或生命维持应用，因为这类应用可能需要更高的可靠性标准。版本历史记录显示，该数据手册的版本号为SP-1.2，最后更新日期为2011年6月20日，表明GainSpan可能会定期发布新的修订版以反映产品改进和更新。 GS1011M数据手册是开发者和工程师设计基于Wi-Fi功能产品的关键参考资料，它提供了所有必要的信息来集成这款低功耗Wi-Fi模块到各种物联网设备中。

GS1011M

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2 Architecture

2.1 G1011Mxx Block Diagram

Figure 2-1: GS1011MIx Block Diagram

Figure 2-2: GS1011MEx Block Diagram

GS1011M

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2.2 Block Diagram Description

2.2.1 Overview

GS1011Mxx module is a highly integrated ultra low power Wi-Fi system-on-chip (SOC) that contains

the following:

• The module includes GS1011 SoC, which contains media access controller (MAC), baseband

processor, security, on-chip flash memory and SRAM, and an applications processor in a single

package.

• The module contains two ARM7-based processors, one dedicated to Networking Subsystems,

and the other dedicated to Wireless Subsystems.

• The module carries an 802.11 radio with onboard 32 KHz & 44 MHz crystal circuitries, RF, and

certified PCB antenna or external antenna options.

o The low power module option has a capability of +9dBm output power at the antenna

(see Figure 2-1).

o The extended range module option has a capability of +17dBm output power at the an-

tenna (see Figure 2-2).

• Variety of interfaces are available such as two UART blocks using only two data lines per port

with optional hardware flow controls, two SPI block (one dedicated as a serial slave with confi-

gurable hardware interrupt to the HOST), I

C with Master or slave operation, JTAG port, low-

power 10-bit ADC capable of running at up to 32 Ksamples/Sec., GPIO’s, and LED Driv-

ers/GPIO with 20mA capabilities.

• GS1011Mxx contains single power supply (VIN_3V3) with optional module controlled external

regulator enable control pin (DC_DC_CNTL), a separate I/O supply (VDDIO) that can be tied to

the HOST supply rail without the use of external voltage translators, Real Time Clock (RTC)

with battery supply monitor option (VBAT), and two external alarm inputs enable wake-up of

the system on external events & outputs (ALARM and RTC_OUT) to enable periodic wake-up

of the remainder of the system.

o The Module carries onboard single supply monitor for under voltage supply and onboard

1.8V regulator with enable/disable capabilities for power critical applications.

2.2.2 Wireless Subsystem

The Wireless subsystem provides the WLAN PHY, MAC and baseband functionality. It contains the

WLAN CPU, a 32-bit ARM7 TDMI-S core running at up to 44 MHz. It includes an IEEE 802.11b/g -

compatible RF transceiver, which supports Direct Sequence Spread Spectrum (DSSS) 1 Mb/s and 2 Mb/s

data rates, and Complementary Code Keyed (CCK) 5.5 Mb/s and 11 Mb/s data rates. The WLAN sub-

system includes an integrated power amplifier, and provides management capabilities for an optional

external power amplifier. In addition, it contains hardware support for AES-CCMP encryption (for

WPA2) and RC4 encryption (for WEP & WPA/WPA2 TKIP) encryption/decryption.

The WLAN subsystem contains the control logic and state machines required to drive the low power

DSSS modem, and perform pre-processing (in transmit mode) or post-processing (in receive mode) of

the data stream. The WLAN subsystem manages DMA accesses, data encryption/decryption using the

AES algorithm, and CRC computation.

GS1011M

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2.2.2.1 Onboard antenna / RF port / Radio

The GS1011Mxx modules have fully integrated RF frequency synthesizer, reference clock, low power

PA, and high power PA for extended range applications. Both TX and RX chain in the module incorpo-

rate internal power control loops. The GS1011Mxx modules also incorporate onboard printed antenna

option plus a variety of regulatory certified antenna options for various application needs.

2.2.3 Network Subsystem

2.2.3.1 APP CPU

The APP CPU is an ARM7 TDMI-S. It incorporates an AHB interface and a JTAG debug interface. The

network RTOS, network stack, and customer application code can reside on this CPU. For more infor-

mation, consult the GS1011 Peripheral and Register Description [2] and GS1011 SoC data sheet [3] for

detailed descriptions.

2.2.4 Memory Subsystem

2.2.4.1 Overview

The GS1011 Chip contains several memory blocks:

►

Boot ROM blocks.

►

The software contained in this ROM provides the capability to download new firmware via

the SPI Slave or UART interfaces and to control the update of WLAN and APP Flash Memo-

ry.

►

384 KBytes of Embedded Flash to store program code.

►

Three embedded Flash blocks of 128K bytes each

►

WLAN Flash (contains the WLAN Software)

►

APP Flash 0 and 1 (contain the Network/Application Software)

►

128 KBytes of RAM shared between the two integrated CPU’s.

►

512 bytes of RTC memory ((retains data in all states including Standby, as long as the battery or

other voltage supply is present)

For more information, consult the GS1011 Peripheral and Register Description [2] and GS1011 IC data

sheet [3] for detailed descriptions.

2.2.5 Clock Circuitries

The GS1011MXX architecture uses a low-power oscillator (i.e. 32 kHz) to provide a minimal subset of

functions when the chip is in its low-power Standby mode, and a high-speed 44 MHz oscillator to pro-

vide clock signals for the processors, bus, and interfaces during active operation. Intermediate modes of

operation, in which the 44 MHz oscillator is active but some modules are inactive, are obtained by gating

the clock signal to different subsystems. The Clock & Reset Controller, within the device, is responsible

for generation, selection and gating of the clocks used in the module to reduce power consumption in

various power states.

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