VHDL经典例程集：探索语言的强大与多样性

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VHDL语言例程集锦是一份由Ian Elliot撰写，来自诺森比亚大学的专业资料，旨在展示VHDL（Vera Holladay Design Language）在电子设计自动化中的多样性和强大功能。VHDL是一种广泛应用于硬件描述语言，它被用于描述不同类型的硬件系统，从简单的组合逻辑到复杂的微处理器模型和相关存储器。这份文档包含了丰富的VHDL源代码示例，涵盖了多个主题，包括： 1. **组合逻辑 (Combinational Logic)**: 通过基本逻辑门如与门、或门和非门来介绍基础概念，如一个数据流风格的异或门（Exclusive-OR Gate）。 2. **计数器 (Counters)**: 提供了不同类型的计数器设计，这对于数字电路设计非常重要，尤其是在时序逻辑中。 3. **移位寄存器 (Shift Registers)**: 学习如何使用VHDL描述数据的存储和移动，这是通信和数据处理的关键组成部分。 4. **内存 (Memory)**: 包括存储器模块的设计，如RAM和ROM，对于构建具有记忆功能的系统至关重要。 5. **状态机 (State Machines)**: 展示了状态机的设计，这是一种强大的抽象工具，用于描述基于状态的行为。 6. **寄存器 (Registers)**: 不同类型和功能的寄存器，如通用寄存器和特殊功能寄存器，是数字系统的核心组件。 7. **系统 (Systems)**: 高级示例涉及整个系统的描述，如模拟-数字转换器（ADC）和数字-模拟转换器（DAC），以及算术运算单元。 8. **其他逻辑门 (Miscellaneous Logic Gates)**: 提供了各种特殊逻辑门的设计，如三输入多数表决器和幅度比较器。 9. **特定集成电路 (ICs) 实现**: 如74x00系列的四输入与非门，以及BCD码到七段显示译码器和双2-4译码器等。 10. **接口电路 (Interfacing)**: 探讨了如何将这些电路与其他数字和模拟电路连接起来，比如八进制总线传输器。这些示例不仅可以帮助初学者理解VHDL的基础结构和语法规则，还能展示如何将理论知识应用到实际的电子设计中。每个例子都提供了足够的详细说明，以便于模拟和合成，以便工程师们可以将其直接运用到他们的项目中。无论你是刚入门的VHDL新手还是经验丰富的设计师，这份资料都是宝贵的参考资料和实践案例库。

Examples of VHDL Descriptions

tin(i) <= '1';

end generate;

t1_size : if i > 0 generate

tin(i) <= q(i-1) and tin(i-1);

end generate;

end v1;

Counter using Multiple Wait Statements

This example shows an inefficient way of describing a counter.

--vhdl model of a 3-state counter illustrating the use

--of the WAIT statement to suspend a process.At each wait

--statement the simulation time is updated one cycle,transferring

--the driver value to the output count.

--This architecture shows that there is no difference between

--WAIT UNTIL (clock'EVENT AND clock = '1') and WAIT UNTIL clock = '1'

ENTITY cntr3 IS

PORT(clock : IN BIT; count : OUT NATURAL);

END cntr3;

ARCHITECTURE using_wait OF cntr3 IS

BEGIN

PROCESS

BEGIN

--WAIT UNTIL (clock'EVENT AND clock = '1');

WAIT UNTIL clock = '1';

count <= 0;

--WAIT UNTIL (clock'EVENT AND clock = '1');

WAIT UNTIL clock = '1';

count <= 1;

--WAIT UNTIL (clock'EVENT AND clock = '1');

WAIT UNTIL clock = '1';

count <= 2;

END PROCESS;

END using_wait;

Counter using a Conversion Function

This counter uses a natural number to hold the count value and converts it into a bit_vector for output. Illustrates the use of a function.

--4-bit binary up counter with asynchronous reset 2/2/93

ENTITY cntr4bit IS

PORT(reset,clock : IN BIT; count : OUT BIT_VECTOR(0 TO 3));

END cntr4bit;

ARCHITECTURE dataflow OF cntr4bit IS

--interface function to generate output bit_vector from

--internal count value.

FUNCTION nat_to_bv(input : NATURAL; highbit : POSITIVE)

RETURN BIT_VECTOR IS

VARIABLE temp : NATURAL := 0;

VARIABLE output : BIT_VECTOR(0 TO highbit);

BEGIN

temp := input;

--check that input fits into (highbit+1) bits

ASSERT (temp <= (2**(highbit + 1) - 1))

REPORT "input no. is out of range" SEVERITY ERROR;

http://www.ami.bolton.ac.uk/courseware/adveda/vhdl/vhdlexmp.html (12 of 67) [23/1/2002 4:15:08 ]

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Examples of VHDL Descriptions

--generate bit values

FOR i IN highbit DOWNTO 0 LOOP

IF temp >= (2**i)

THEN output(i) := '1';

temp := temp - (2**i);

ELSE output(i) := '0';

END IF;

END LOOP;

RETURN output;

END nat_to_bv;

--signal to hold current count value

SIGNAL intcount : NATURAL := 0;

BEGIN

--conditional natural signal assignment models counter

intcount <= 0 WHEN (reset = '1') ELSE

((intcount + 1) MOD 16) WHEN (clock'EVENT AND clock = '1')

ELSE intcount;

--interface function converts natural count to bit_vector count

count <= nat_to_bv(intcount,3);

END;

Quad 2-input Nand

Simple concurrent model of a TTL quad nand gate.

--uses 1993 std VHDL

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT00 is

port(A1, B1, A2, B2, A3, B3, A4, B4 : in std_logic;

Y1, Y2, Y3, Y4 : out std_logic);

end HCT00;

architecture VER1 of HCT00 is

begin

Y1 <= A1 nand B1 after 10 ns;

Y2 <= A2 nand B2 after 10 ns;

Y3 <= A3 nand B3 after 10 ns;

Y4 <= A4 nand B4 after 10 ns;

end VER1;

Dual 2-to-4 Decoder

A set of conditional signal assignments model a dual 2-to-4 decoder

--uses 1993 std VHDL

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT139 is

port(A2, B2, G2BAR, A1, B1, G1BAR : in std_logic;

Y20, Y21, Y22, Y23, Y10, Y11, Y12, Y13 : out std_logic);

end HCT139;

architecture VER1 of HCT139 is

begin

Y10 <= '0' when (B1 = '0') and ((A1 = '0') and (G1BAR = '0')) else '1';

Y11 <= '0' when (B1 = '0') and ((A1 = '1') and (G1BAR = '0')) else '1';

Y12 <= '0' when (B1 = '1') and ((A1 = '0') and (G1BAR = '0')) else '1';

Y13 <= '0' when (B1 = '1') and ((A1 = '1') and (G1BAR = '0')) else '1';

Y20 <= '0' when (B2 = '0') and ((A2 = '0') and (G2BAR = '0')) else '1';

http://www.ami.bolton.ac.uk/courseware/adveda/vhdl/vhdlexmp.html (13 of 67) [23/1/2002 4:15:08 ]

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Examples of VHDL Descriptions

Y21 <= '0' when (B2 = '0') and ((A2 = '1') and (G2BAR = '0')) else '1';

Y22 <= '0' when (B2 = '1') and ((A2 = '0') and (G2BAR = '0')) else '1';

Y23 <= '0' when (B2 = '1') and ((A2 = '1') and (G2BAR = '0')) else '1';

end VER1;

Quad D-Type Flip-flop

This example shows how a conditional signal assignment statement could be used to describe sequential logic (it is more common to use a process). The keyword 'unaffected' is equivalent to the 'null' statement in the sequential part

of the language. The model would work exactly the same without the clause 'else unaffected' attached to the end of the statement.

--uses 1993 std VHDL

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT175 is

port(D : in std_logic_vector(3 downto 0);

Q : out std_logic_vector(3 downto 0);

CLRBAR, CLK : in std_logic);

end HCT175;

architecture VER1 of HCT175 is

begin

Q <= (others => '0') when (CLRBAR = '0')

else D when rising_edge(CLK)

else unaffected;

end VER1;

Octal Bus Transceiver

This example shows the use of the high impedance literal 'Z' provided by std_logic. The aggregate '(others => 'Z')' means all of the bits of B must be forced to 'Z'. Ports A and B must be resolved for this model to work correctly (hence std_logic rather than

std_ulogic).

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT245 is

port(A, B : inout std_logic_vector(7 downto 0);

DIR, GBAR : in std_logic);

end HCT245;

architecture VER1 of HCT245 is

begin

A <= B when (GBAR = '0') and (DIR = '0') else (others => 'Z');

B <= A when (GBAR = '0') and (DIR = '1') else (others => 'Z');

end VER1;

Quad 2-input OR

--uses 1993 std VHDL

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT32 is

port(A1, B1, A2, B2, A3, B3, A4, B4 : in std_logic;

Y1, Y2, Y3, Y4 : out std_logic);

end HCT32;

architecture VER1 of HCT32 is

begin

Y1 <= A1 or B1 after 10 ns;

Y2 <= A2 or B2 after 10 ns;

Y3 <= A3 or B3 after 10 ns;

Y4 <= A4 or B4 after 10 ns;

http://www.ami.bolton.ac.uk/courseware/adveda/vhdl/vhdlexmp.html (14 of 67) [23/1/2002 4:15:08 ]

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