"SMJ320F2812 DSP芯片说明书及datasheet"

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The DSP chip SMJ320F2812 is a high-performance digital signal processor designed for applications that require fast and efficient signal processing. It is built using high-performance static CMOS technology, allowing for a clock speed of up to 150 MHz with a cycle time of 6.67 ns. This chip is also designed to be low-power, consuming only 1.8 volts during operation. The datasheet for the SMJ320F2812 DSP chip provides detailed information on its features, specifications, and performance characteristics. It includes information on the processor's architecture, instruction set, memory organization, and I/O capabilities. The datasheet also provides guidelines for programming and using the chip in various applications. The SM320F2812 DSP chip is a versatile processor that can be used in a wide range of applications, including audio processing, motor control, communications, and instrumentation. Its high-speed performance and low-power consumption make it ideal for applications that require real-time signal processing. Overall, the SMJ320F2812 DSP chip is a powerful and efficient processor that offers high performance and low power consumption. Its versatility and advanced features make it a great choice for a wide range of signal processing applications. Whether you are designing audio systems, control systems, or communication devices, the SMJ320F2812 DSP chip is a versatile and reliable solution.

Functional Overview

December 2004 − Revised September 2006 SGUS053B

Table 3−1. Addresses of Flash Sectors in F2812

ADDRESS RANGE PROGRAM AND DATA SPACE

0x3D 8000

0x3D 9FFF

Sector J, 8K x 16

0x3D A000

0x3D BFFF

Sector I, 8K x 16

0x3D C000

0x3D FFFF

Sector H, 16K x 16

0x3E 0000

0x3E 3FFF

Sector G, 16K x 16

0x3E 4000

0x3E 7FFF

Sector F, 16K x 16

0x3E 8000

0x3E BFFF

Sector E, 16K x 16

0x3E C000

0x3E FFFF

Sector D, 16K x 16

0x3F 0000

0x3F 3FFF

Sector C, 16K x 16

0x3F 4000

0x3F 5FFF

Sector B, 8K x 16

0x3F 6000 Sector A, 8K x 16

0x3F 7F80

0x3F 7FF5

Program to 0x0000 when using the

Code Security Module

0x3F 7FF6

0x3F 7FF7

Boot-to-Flash (or ROM) Entry Point

(program branch instruction here)

0x3F 7FF8

0x3F 7FFF

Security Password (128-Bit)

(Do not program to all zeros)

Functional Overview

December 2004 − Revised September 2006SGUS053B

The Low 64K of the memory address range maps into the data space of the 240x. The High 64K of the memory

address range maps into the program space of the 24x/240x. 24x/240x-compatible code only executes from

the High 64K memory area. Hence, the top 32K of Flash/ROM and H0 SARAM block can be used to run

24x/240x-compatible code (if MP/MC mode is low) or, on the 2812, code can be executed from XINTF Zone 7

(if MP/MC mode is high).

The XINTF consists of five independent zones. One zone has its own chip select and the remaining four zones

share two chip selects. Each zone can be programmed with its own timing (wait states) and to either sample

or ignore external ready signal. This makes interfacing to external peripherals easy and glueless.

NOTE:

The chip selects of XINTF Zone 0 and Zone 1 are merged together into a single chip select

(XZCS0AND1); and the chip selects of XINTF Zone 6 and Zone 7 are merged together into

a single chip select (XZCS6AND7). See Section 3.5, External Interface, XINTF (2812 only),

for details.

Peripheral Frame 1, Peripheral Frame 2, and XINTF Zone 1 are grouped together so as to enable these blocks

to be write/read peripheral block protected. The protected mode ensures that all accesses to these blocks

happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different memory

locations, appears in reverse order on the memory bus of the CPU. This can cause problems in certain

peripheral applications where the user expected the write to occur first (as written). The C28x CPU supports

a block protection mode where a region of memory can be protected so as to make sure that operations occur

as written (the penalty is extra cycles are added to align the operations). This mode is programmable and by

default, it protects the selected zones.

On the 2812, at reset, XINTF Zone 7 is accessed if the XMP/MC pin is pulled high. This signal selects

microprocessor or microcomputer mode of operation. In microprocessor mode, Zone 7 is mapped to high

memory such that the vector table is fetched externally. The Boot ROM is disabled in this mode. In

microcomputer mode, Zone 7 is disabled such that the vectors are fetched from Boot ROM. This allows the

user to either boot from on-chip memory or from off-chip memory. The state of the XMP/MC signal on reset

is stored in an MP/MC mode bit in the XINTCNF2 register. The user can change this mode in software and

hence control the mapping of Boot ROM and XINTF Zone 7. No other memory blocks are affected by

XMP/MC.

I/O space is not supported on the 2812 XINTF.

The wait states for the various spaces in the memory map area are listed in Table 3−2.

Functional Overview

December 2004 − Revised September 2006 SGUS053B

Table 3−2. Wait States

AREA WAIT-STATES COMMENTS

M0 and M1 SARAMs 0-wait Fixed

Peripheral Frame 0 0-wait Fixed

Peripheral Frame 1

0-wait (writes)

2-wait (reads)

Fixed

Peripheral Frame 2

0-wait (writes)

2-wait (reads)

Fixed

L0 & L1 SARAMs 0-wait

OTP (or ROM)

Programmable,

1-wait minimum

Programmed via the Flash registers. 1-wait-state operation is possible at a

reduced CPU frequency. See Section 3.2.6, Flash (F281x Only), for more

information.

Flash (or ROM)

Programmable,

0-wait minimum

Programmed via the Flash registers. 0-wait-state operation is possible at

reduced CPU frequency. The CSM password locations are hardwired for

16 wait-states. See Section 3.2.6, Flash (F281x Only), for more information.

H0 SARAM 0-wait Fixed

Boot-ROM 1-wait Fixed

XINTF

Programmable,

1-wait minimum

Programmed via the XINTF registers.

Cycles can be extended by external memory or peripheral.

0-wait operation is not possible.

3.2 Brief Descriptions

3.2.1 C28x CPU

The C28x™ DSP generation is the newest member of the TMS320C2000™ DSP platform. The C28x is source

code compatible to the 24x/240x DSP devices, hence existing 240x users can leverage their significant

software investment. Additionally, the C28x is a very efficient C/C++ engine, hence enabling users to develop

not only their system control software in a high-level language, but also enables math algorithms to be

developed using C/C++. The C28x is as efficient in DSP math tasks as it is in system control tasks that typically

are handled by microcontroller devices. This efficiency removes the need for a second processor in many

systems. The 32 x 32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the C28x

to efficiently handle higher numerical resolution problems that would otherwise demand a more expensive

floating-point processor solution. Add to this the fast interrupt response with automatic context save of critical

registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency.

The C28x has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables

the C28x to execute at high speeds without resorting to expensive high-speed memories. Special

branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional

operations further improve performance.

C28x and TMS320C2000 are trademarks of Texas Instruments.

Functional Overview

December 2004 − Revised September 2006SGUS053B

3.2.2 Memory Bus (Harvard Bus Architecture)

As with many DSP type devices, multiple busses are used to move data between the memories and

peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus

and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and

write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single

cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to

fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and memories

attached to the memory bus prioritizes memory accesses. Generally, the priority of Memory Bus accesses can

be summarized as follows:

Highest: Data Writes

†

Program Writes

†

Data Reads

Program Reads

‡

Lowest: Fetches

‡

3.2.3 Peripheral Bus

To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, the F2812

adopts a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the

various busses that make up the processor Memory Bus into a single bus consisting of 16 address lines and

16 or 32 data lines and associated control signals. Two versions of the peripheral bus are supported on the

F2812. One version only supports 16-bit accesses (called peripheral frame 2) and this retains compatibility

with C240x-compatible peripherals. The other version supports both 16- and 32-bit accesses (called

peripheral frame 1).

3.2.4 Real-Time JTAG and Analysis

The F281x implement the standard IEEE 1149.1 JTAG interface. Additionally, the F2812 supports real-time

mode of operation whereby the contents of memory, peripheral and register locations can be modified while

the processor is running and executing code and servicing interrupts. The user can also single step through

non-time critical code while enabling time-critical interrupts to be serviced without interference. The F2812

implements the real-time mode in hardware within the CPU. This is a unique feature to the F2812, no software

monitor is required. Additionally, special analysis hardware is provided which allows the user to set hardware

breakpoint or data/address watch-points and generate various user selectable break events when a match

occurs.

3.2.5 External Interface (XINTF)

This asynchronous interface consists of 19 address lines, 16 data lines, and three chip-select lines. The

chip-select lines are mapped to five external zones, Zones 0, 1, 2, 6, and 7. Zones 0 and 1 share a single

chip-select; Zones 6 and 7 also share a single chip-select. Each of the five zones can be programmed with

a different number of wait states, strobe signal setup and hold timing and each zone can be programmed for

extending wait states externally or not. The programmable wait-state, chip-select, and programmable strobe

timing enables glueless interface to external memories and peripherals.

†

Simultaneous Data and Program writes cannot occur on the Memory Bus.

‡

Simultaneous Program Reads and Fetches cannot occur on the Memory Bus.

Functional Overview

December 2004 − Revised September 2006 SGUS053B

3.2.6 Flash

The F2812 contains 128K x 16 of embedded flash memory, segregated into four 8K X 16 sectors, and six 16K

X 16 sectors. The F2810 has 64K X 16 of embedded flash, segregated into two 8K X 16 sectors, and three

16K X 16 sectors. The device also contains a single 1K x 16 of OTP memory at address range 0x3D 7800

− 0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving other sectors

untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash algorithms

that erase/program other sectors. Special memory pipelining is provided to enable the flash module to achieve

higher performance. The flash/OTP is mapped to both program and data space; therefore, it can be used to

execute code or store data information.

NOTE:

The F2812 Flash and OTP wait states can be configured by the application. This allows

applications running at slower frequencies to configure the flash to use fewer wait states.

Flash effective performance can be improved by enabling the flash pipeline mode in the Flash

options register. With this mode enabled, effective performance of linear code execution is

much faster than the raw performance indicated by the wait state configuration alone. The

exact performance gain when using the Flash pipeline mode is application-dependent. The

pipeline mode is not available for the OTP block.

For more information on the Flash options, Flash wait-state, and OTP wait-state registers, see

the TMS320x281x System Control and Interrupts Reference Guide (SPRU078).

3.2.7 L0, L1, H0 SARAMs

The F281x contains an additional 16K x 16 of single-access RAM, divided into three blocks (4K + 4K + 8K).

Each block can be independently accessed hence minimizing pipeline stalls. Each block is mapped to both

program and data space.

3.2.8 Boot ROM

The Boot ROM is factory-programmed with boot-loading software. The Boot ROM program executes after

device reset and checks several GPIO pins to determine which boot mode to enter. For example, the user can

select to execute code already present in the internal Flash or download new software to internal RAM through

one of several serial ports. Other boot modes exist as well. The Boot ROM also contains standard tables, such

as SIN/COS waveforms, for use in math-related algorithms. Table 3−3 shows the details of how various boot

modes may be invoked. See the TMS320x281x DSP Boot ROM Reference Guide (SPRS095), for more

information.

Table 3−3. Boot Mode Selection

BOOT MODE SELECTED

GPIOF4

(SCITXDA)

GPIOF12

(MDXA)

GPIOF3

(SPISTEA)

GPIOF2

(SPICLK)

GPIO PU status

†

PU No PU No PU No PU

Jump to Flash/ROM address 0x3F 7FF6

A branch instruction must have been programmed here prior to

reset to redirect code execution as desired.

1 x x x

Call SPI_Boot to load from an external serial SPI EEPROM 0 1 x x

Call SCI_Boot to load from SCI-A 0 0 1 1

Jump to H0 SARAM address 0x3F 8000 0 0 1 0

Jump to OTP address 0x3D 7800 0 0 0 1

Call Parallel_Boot to load from GPIO Port B 0 0 0 0

†

PU = pin has an internal pullup. No PU = pin does not have an internal pullup

‡

Extra care must be taken due to any effect toggling SPICLK to select a boot mode may have on external logic.

If the boot mode selected is Flash, H0, or OTP, then no external code is loaded by the bootloader.

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