DDR2 SDRAM内存详解：MT47H系列容量与特性

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DDR2 SDRAM (Double Data Rate Second Generation Synchronous Dynamic Random Access Memory) 是一种高速内存技术，它在数据传输时能够同时读写，显著提高了存储器的带宽。给定的几个型号MT47H256M4、MT47H128M8和MT47H64M16是不同容量和配置的DDR2 SDRAM芯片。首先，这些内存模块的关键规格如下： - **容量**: MT47H256M4提供32兆(Meg) x 4位宽，MT47H128M8提供16兆 x 8位宽，而MT47H64M16则为8兆 x 16位宽。这里的"x4", "x8", 和 "x16" 表示内存总线宽度，即数据线的数量。 - **电压**: DDR2 SDRAM工作于+1.8V±0.1V的电源电压，VDDQ同样如此，确保了兼容性和稳定性。 - **接口标准**: 符合JEDEC标准，支持SSTL_18兼容的1.8V I/O，提供了差分数据 strobe (DQS) 和 DQS#选项，有助于同步数据传输。 - **内部结构**: 采用4n-bit预取架构，对于x8配置还具备读取数据锁存信号 (RDQS) 选项，有助于优化性能。 - **内存银行**: 内部有8个独立的银行，允许并行操作，提高了效率。 - **控制特性**: 可编程CAS (Column Address Strobe) 时延 (CL)，POSTED CAS附加时延 (AL)，以及WRITE与READ时延的设定关系（WRITE = READ - 1tCK）。 - **突发长度 (BL)**：支持4位或8位突发模式，增加了灵活性。 - **输出驱动强度**：可调节，适应不同的系统需求。 - **刷新周期**: 64毫秒，8192周期的刷新，保持数据的稳定存储。 - **其他选项**: 包括On-Die Determination (ODT) 工艺、工业温度等级 (IT) 可选、RoHS合规以及对JEDEC时钟偏差规格的支持。 - **封装形式**: 提供FBGA封装，包括Pb-free选项，如84球的x16尺寸，以及不同尺寸的x4和x8版本，且有些版本带有leadsolder选项。这些信息展示了DDR2 SDRAM的规格特性，对于选择和使用这类内存组件在现代计算机系统中的应用设计至关重要，尤其是在处理高性能计算、图形处理和多任务环境中的数据传输和存储优化。理解这些参数有助于系统设计师做出最佳内存配置决策，以满足特定应用对速度、容量和可靠性的要求。

Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View)

DDQ

DQ15

DDQ

DQ13

DDQ

DQ7

DDQ

DQ5

ODT

UDQS#/NU

SSQ

DQ8

SSQ

LDQS#/NU

SSQ

DQ0

SSQ

CK#

CS#

RFU

SSQ

UDQS

DDQ

DQ10

SSQ

LDQS

DDQ

DQ2

SSDL

RAS#

CAS#

A11

RFU

UDM

DDQ

DQ11

LDM

DDQ

DQ3

WE#

BA1

RFU

SSQ

DQ9

SSQ

DQ1

SSQ

REF

CKE

BA0

A10

A12

DQ14

DDQ

DQ12

DQ6

DDQ

DQ4

DDL

BA2

1 2 3 4 6 7 8 95

1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

PDF: 09005aef821ae8bf

1GbDDR2.pdf – Rev. T 02/10 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions

Symbol Type Description

A[12:0] (x16)

,A[13:0] (x4, x8)

Input

Address inputs: Provide the row address for ACTIVATE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out

of the memory array in the respective bank. A10 sampled during a PRECHARGE com-

mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected

by BA[2:0] or all banks (A10 HIGH). The address inputs also provide the op-code during a

LOAD MODE command.

BA[2:0] Input

Bank address inputs: BA[2:0] define to which bank an ACTIVATE, READ, WRITE, or PRE-

CHARGE command is being applied. BA[2:0] define which mode register, including MR,

EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE command.

CK, CK# Input

Clock: CK and CK# are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and negative edge of CK#. Output

data (DQ and DQS/DQS#) is referenced to the crossings of CK and CK#.

CKE Input

Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates

clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is

dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides

precharge power-down and SELF REFRESH operations (all banks idle), or ACTIVATE power-

down (row active in any bank). CKE is synchronous for power-down entry, power-down

exit, output disable, and for self refresh entry. CKE is asynchronous for self refresh exit.

Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during power-down. Input

buffers (excluding CKE) are disabled during self refresh. CKE is an SSTL_18 input but will

detect a LVCMOS LOW level after V

is applied during first power-up. After V

REF

has

become stable during the power-on and initialization sequence, it must be maintained

for proper operation of the CKE receiver. For proper SELF REFRESH operation, V

REF

must

be maintained.

CS# Input

Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command

decoder. All commands are masked when CS# is registered high. CS# provides for exter-

nal bank selection on systems with multiple ranks. CS# is considered part of the com-

mand code.

LDM, UDM, DM Input

Input data mask: DM is an input mask signal for write data. Input data is masked when

DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on

both edges of DQS. Although DM balls are input-only, the DM loading is designed to

match that of DQ and DQS balls. LDM is DM for lower byte DQ[7:0] and UDM is DM for

upper byte DQ[15:8].

ODT Input

On-die termination: ODT (registered HIGH) enables termination resistance internal to

the DDR2 SDRAM. When enabled, ODT is only applied to each of the following balls:

DQ[15:0], LDM, UDM, LDQS, LDQS#, UDQS, and UDQS# for the x16; DQ[7:0], DQS, DQS#,

RDQS, RDQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input

will be ignored if disabled via the LOAD MODE command.

RAS#, CAS#, WE# Input

Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being

entered.

DQ[15:0] (x16)

DQ[3:0] (x4)

DQ[7:0] (x8)

I/O

Data input/output: Bidirectional data bus for 64 Meg x 16.

Bidirectional data bus for 256 Meg x 4.

Bidirectional data bus for 128 Meg x 8.

1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

PDF: 09005aef821ae8bf

1GbDDR2.pdf – Rev. T 02/10 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions (Continued)

Symbol Type Description

DQS, DQS# I/O

Data strobe: Output with read data, input with write data for source synchronous oper-

ation. Edge-aligned with read data, center-aligned with write data. DQS# is only used

when differential data strobe mode is enabled via the LOAD MODE command.

LDQS, LDQS# I/O

Data strobe for lower byte: Output with read data, input with write data for source

synchronous operation. Edge-aligned with read data, center-aligned with write data.

LDQS# is only used when differential data strobe mode is enabled via the LOAD MODE

command.

UDQS, UDQS# I/O

Data strobe for upper byte: Output with read data, input with write data for source

synchronous operation. Edge-aligned with read data, center-aligned with write data.

UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE

command.

RDQS, RDQS# Output

Redundant data strobe: For x8 only. RDQS is enabled/disabled via the LOAD MODE com-

mand to the extended mode register (EMR). When RDQS is enabled, RDQS is output with

read data only and is ignored during write data. When RDQS is disabled, ball B3 becomes

data mask (see DM ball). RDQS# is only used when RDQS is enabled and differential data

strobe mode is enabled.

Supply

Power supply: 1.8V ±0.1V.

DDQ

Supply

DQ power supply: 1.8V ±0.1V. Isolated on the device for improved noise immunity.

DDL

Supply

DLL power supply: 1.8V ±0.1V.

REF

Supply SSTL_18 reference voltage (V

DDQ

/2).

Supply Ground.

SSDL

Supply

DLL ground: Isolated on the device from V

and V

SSQ

Supply

DQ ground: Isolated on the device for improved noise immunity.

–

No connect: These balls should be left unconnected.

–

No function: x8: these balls are used as DQ[7:4]; x4: they are no function.

–

Not used: For x16 only. If EMR(E10) = 0, A8 and E8 are UDQS# and LDQS#. If EMR(E10) =

1, then A8 and E8 are not used.

–

Not used: For x8 only. If EMR(E10) = 0, A2 and E8 are RDQS# and DQS#. If EMR(E10) = 1,

then A2 and E8 are not used.

RFU

–

Reserved for future use: Row address bits A13 (x16 only), A14, and A15.

1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

PDF: 09005aef821ae8bf

1GbDDR2.pdf – Rev. T 02/10 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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