AR0233AT 1_2.5寸CMOS数字图像传感器开发者指南

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AR0233AT是一款由ON Semiconductor设计的1/2.5英寸CMOS数字图像传感器，专为高级驾驶辅助系统（ADAS）、环绕视图、后视镜替换（CMS）等应用提供高性能解决方案。该传感器具有以下关键特性： 1. 高动态范围（HDR）RAW输出：AR0233AT支持高达24位（超过140分贝）的HDR图像处理，这对于捕捉宽广的动态范围场景至关重要，确保了在明亮和阴暗区域都能保持细节清晰。 2. 多模式曝光控制：传感器支持全分辨率的120dB三阶曝光（3Exp HDR），结合T1超级曝光和T2线性模式，使得摄影师能够在不同光照条件下实现灵活的曝光设置。 3. 高性能3微米像素：AR0233AT采用新型3微米背照式（BSI）像素技术，结合超级曝光HDR和低频脉冲（LFM）模式，提升了图像质量和处理速度。 4. 高级HDR图像组合：传感器具备先进的HDR图像组合功能，允许用户通过灵活的曝光比控制，实时合成出更丰富的视觉效果。 5. 高分辨率与多功能性：图像传感器拥有2048行x1280列的有效像素，能提供高清晰度的图像，并且适用于多种应用场景，如ADAS视图融合。开发指南文档详细介绍了这款传感器的各种功能特性和使用方法，包括电气规格、时序参数以及寄存器描述，旨在帮助开发者充分利用其性能潜力。为了获取完整的规格信息和详细操作指南，建议参考AR0233AT的数据手册和注册参考文档。 AR0233AT作为一款高性能图像传感器，对于追求高质量影像和复杂应用场景的设计师和开发者来说，提供了强大的工具和灵活性。通过深入理解并掌握其特性，用户能够优化图像捕获和处理过程，确保在各种照明条件下获得最佳的视觉效果。

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Context Select Example

Select Context 0, R0x3034 set to 0x8000

Select Context 2, R0x3034 set to 0x8002

SENSOR PLL

VCO

The sensor contains a phase−locked loop (PLL) that is

used for timing generation and control. The required VCO

clock frequency is attained through the use of a pre−PLL

clock divider followed by a multiplier. The multiplier is

followed by a set of dividers used to generate the output

clocks required for the sensor array, the pixel analog and

digital readout paths, and the output serial interfaces. Use of

the PLL is required when using the MIPI interface.

PRE

_PLL_

DIV

VCO

PLL

_MULT

P1Divider P2

Divider

P3Divider P4Divider

VCO

DIV

FREF

PIC

_CLOCK

WORD

CLOCK

BIT_CLOCK

16−4095

1−63 1/2/4/8

1/2/4/8

4−16

1/2/4/8

Figure 2. PLL Interface

PLL CONFIGURATION

The PLL must be enabled when MIPI mode is selected.

The sensor will use op_sys_clk_div and op_pix_clk_div to

configure the output bit clock (Fserial) and word clock per

lane(CLK_OP). The configuration will depend on the

number of active lanes (1, 2, or 4) to be used and data bit

depth (12, 14, 16, 20 and 24).

PLL can be calculated using the following equation:

FVCO +

Extclk x * pll

multiplier

* vcodiv

pre_pll_clk_div

(eq. 1)

clk_pix +

FVCO

vt_sys_clk_div(P1) * vt_pix_clk_div(P2) * vcodiv

(eq. 2)

clk_word +

FVCO

op_sys_clk_div(P3) * op_word_clk_div(P4) * vcodiv

(eq. 3)

RESOLUTION _WINDOW CONTROL

ON Semiconductor’s AR0233AT sensor is capable of a

maximum resolution of 2048H x1280V at up to 45fps in

3Exp−HDR mode and 60 fps in 1080P T1 SE + T2 Lin mode.

Registers y_addr_start(R0x3002), x_addr_start(R0x3004),

y_addr_end(R0x3006), and x_addr_end(0x3008) are used

to specify the image window. The minimum value for

x_addr_start is 0 and the maximum x_addr_end is 2063. The

minimum y_addr_start and maximum y_addr_end are 0 and

1287, respectively.

BLANKING CONTROL

Horizontal blanking is not specified for AR0233AT. But,

minimum line_length_pck can be presented that is

determined based upon 4 different limitation which are

dependent upon the desired number of exposures. The

categories for the limitations are: Sequencer Limited,

Column Readout Limited, Sensor Core Limited, and Output

Data Path Limited. Please refer to the Register Wizard to

determine minimum line_length_pck.

Vertical blanking is specified in terms of number of lines.

It is calculated by subtracting the Y window size from the

frame_length_lines register. The minimum vertical

blanking is 40 lines.

IMAGE ACQUISITION MODES

Electronic Rolling Shutter (ERS) Mode. This is the

normal mode of operation. When the AR0233AT is

streaming, it generates frames at a fixed rate, and each frame

is integrated (exposed) using the ERS. When the ERS is in

use, timing and control logic within the sensor sequences

through the rows of the array, resetting and then reading each

row in turn. In the time interval between resetting a row and

subsequently reading that row, the pixels in the row integrate

incident light. The integration (exposure) time is controlled

by varying the time between row reset and row readout. For

each row in a frame, the time between row reset and row

readout is the same, leading to a uniform integration time

across the frame. When the integration time is changed (by

using the two−wire serial interface to change register

settings), the timing and control logic controls the transition

from old to new integration time in such a way that the

stream of output frames from the AR0233AT switches

cleanly from the old integration time to the new while only

generating frames with uniform integration.

TRIGGER MODES

The trigger mode feature of the AR0233AT supports

triggering the start of a frame readout from a VD signal that

is supplied from an external ASIC. The trigger mode signal

allows for precise control of frame rate and register change

updates. The three supported sync modes are: Trigger

Standard, Trigger Deterministic and Trigger Shutter Sync

(Surround View) Modes.

Trigger Standard Mode

To setup Trigger Standard Mode, set 0x30CE [4] = 0, and

0x30CE[5] = 0. At the start. The sensor is in state standby

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and when the input signal TRIGGER is asserted, it transits

to the streaming state, starts the integration time, and outputs

a frame, similarly to setting the stream mode bit via a

two−wire serial interface command. The difference with

normal stream mode is that after the end of frame, the sensor

will automatically go back to standby mode. To keep the

sensor in stream state and capture more frames, the pad

TRIGGER must be kept high.

The sequence of events is as follows:

1. The first trigger pulse generates one frame. The

sensor returns to standby

2. The second assertion of the trigger pad, generates

one frame, but at the end of this frame, the sensor

is kept in stream mode because the pad trigger is

still asserted

The detailed operations for the “FIRST FRAME” after

standby are:

1. Global reset of the pixel array is finished

2. Shutter pointer is started. After the end of

integration time for dark rows, the readout is

started. But, since the dark rows are normally not

output, the frame valid starts when the visible rows

are read

Trigger Deterministic Mode

Before entering Trigger Deterministic mode, it is

important to set 0x30CE [4] = 0 and 0x30CE[5] = 1. In this

mode, after a reception of trigger signal, the sensor will start

a frame length lines (FLL) time period. After the end of this

period, the array read out will start. This means that the read

out start time and frame valid out will be fixed to the trigger

signal.

The difference from the normal stream mode is that after

the end of frame, the sensor will automatically go back to

standby mode. To keep the sensor in stream state and capture

more frames, the pad TRIGGER must be kept high.

This mode is similar to the Trigger standard mode, but that

the readout frame delay is determined by frame_length_line

x line_length_pckclocks.

Note: Max variation is up to 9*Ext_clk cycles to sensor start

of streaming from input signal TRIGGER is asserted in

stereo camera with same setting and TRIGGER signal.

Trigger Shutter Sync (or Surround View Slave) Mode

Trigger Shutter Sync mode is useful for Surround View

applications. This mode is enabled by setting 0x30CE[5]=1

and 0x30CE[8]=1. Upon reception of trigger signal, the

sensor will start a frame length lines (FLL) time period.

After the end of this period, the array read out will start. This

means that the read out start time and frame valid out, will

be fixed to the trigger signal. The sensor logic will start the

shutter pointer before readout to provide the required coarse

integration time (CIT). The required CIT must not be equal

or greater than FLL. In HDR mode, the sum of all exposures

must be less than FLL.

NOTE: It is important that the time between two following

trigger signals is equal or greater than FLL, otherwise the

second trigger will be lost. This is due to fact that the sensor

can’t generate frames faster than FLL.

Programmable Trigger Delay Mode

The Programmable Trigger Delay Mode allows for the

time between the trigger pulse reception and the start of the

frame readout to be delayed to allow for proper syncing of

multi−camera systems.

The sensor needs to be configured in one of the trigger

modes (TRIGGER STANRDARD, TRIGGER

DETERMINISTIC and TRIGGER SHUTTER SYNC) and

have the trigger_delay_mode(R0x30DC[0]) enabled for the

internal trigger rising edge to be delayed. The amount of

delay is concatenation of R0x3400[15:8] and

R0x30DC[15:1] and measured in External clocks since the

sensor is in standby mode before the trigger has been issued.

Table 9. REGISTER LIST FOR TRIGGER MODE CONTROL

Address

Default

Value

Description

Slave_mode R0x30CE[4] 0x0 When set the start of sensor readout will be synchronized with the

external trigger (applied to pad TRIGGER).

Frame_start_mode R0x30CE[5] 0x0 This bit controls the frame timing of the first frame when entering

stream mode (or trigger mode). When low, the integration time is

started and then readout begins. It means that the first frame will start

after a delay equal to CIT. When high, a frame time is started and at

the appropriate time point, the integration starts. It means that the

first frame will start after one frame time.

Slave_sh_sync_mode R0x30CE[8] 0x0 Also called SURROUND VIEW mode. When set and the sensor is

set to stream mode, it waits for an external trigger signal. When a

trigger is received, a time interval of frame length lines is started. The

shutter pointers are started at appropriate point and when this time

interval is finished, the read out is started. The external trigger period

must not be less than frame length lines, otherwise the triggers hap-

pening during the time interval will be ignored.

Trigger_delay_trigger_de-

lay_mode

R0x30DC[0] 0x0 When set Trigger delay mode is enabled.

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