Cypress S25FL116K：高性能SPI闪存记忆体

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"SPI Flash Memory S25FL116K" S25FL116K是一款由Cypress Semiconductor Corporation生产的SPI串行闪存存储器，设计用于满足高速、低功耗的需求，适用于各种嵌入式系统和电子设备。这款SPI闪存提供16Mbit（2Mbyte）、32Mbit（4Mbyte）和64Mbit（8Mbyte）的不同存储容量，支持宽电压范围的3.0V SPI接口。 SPI（Serial Peripheral Interface）是一种常见的通信协议，用于微控制器与外部设备之间进行数据传输。S25FL116K支持SPI的多输入/输出（Multi-I/O）模式，可以使用4线或更多线配置，以提高数据传输速率。它还兼容SPIClock极性和相位模式0和3，这意味着它可以适应不同的系统配置。在读取性能方面，S25FL116K提供了多种读取模式，包括正常读取、快速读取、双倍速读取和四倍速读取。正常读取速度高达50MHz（在-40°C到+85°C或105°C的温度范围内），而快速读取速度可达到108MHz。双倍速和四倍速读取模式进一步提升了速度，尤其是在四倍速读取模式下，对于S25FL164K型号，最高可达97MHz。这使得数据传输速率非常快，最大连续数据传输速率可达54MB/s，在-40°C到+85°C或105°C的温度范围内。此外，S25FL116K支持高效的Execute-In-Place（XIP）功能，允许处理器直接从闪存执行代码，无需将数据加载到RAM，从而节省了系统资源。连续和环绕读取模式则优化了数据流处理，确保无缝的数据访问。S25FL116K还遵循Serial Flash Discoverable Parameters (SFDP) 标准，这是一个行业标准，使设备能被系统自动识别和配置。在编程和擦除功能上，S25FL116K支持串行输入的页编程，一次最多可以编程256字节的数据，并具有编程暂停和恢复功能，方便在编程过程中中断和继续。它采用统一的4KB扇区擦除，确保数据安全且高效地清除。同时，该器件还支持块擦除和全芯片擦除操作，以适应不同级别的数据管理和更新需求。 S25FL116K是面向需要高速、大容量非易失性存储解决方案的应用的理想选择，如嵌入式控制系统、物联网设备、汽车电子、工业自动化和消费电子产品等。其强大的读取速度、灵活的读写模式以及对SPI协议的良好支持，使得它在众多SPI闪存产品中脱颖而出。

Document Number: 002-00497 Rev. *E Page 15 of 90

S25FL116K, S25FL132K, S25FL164K

Figure 3.7 Dual Output Command

Figure 3.8 Quad Output Command without Latency

Figure 3.9 Dual I/O Command

Figure 3.10 Quad I/O Command

Additional sequence diagrams, specific to each command, are provided in Commands on page 63.

CS#

SCK

IO0

IO1

Phase

7 6 5 4 3 2 1 0 23 22 21 0 6 4 2 0 6 4 2 0

7 5 3 1 7 5 3 1

Instruction Dummy Data 1 Data 2

Address

CS#

SCK

IO0

IO1

IO2

IO3

Phase

7 6 5 4 3 2 1 0 23 1 0 4 0 4 0 4 0 4 0 4 0 4

5 1 5 1 5 1 5 1 5 1 5

6 2 6 2 6 2 6 2 6 2 6

7 3 7 3 7 3 7 3 7 3 7

Instruction Address Data 1 Data 2 Data 3 Data 4 Data 5 ...

CS#

SCK

IO0

IO1

Phase

7 6 5 4 3 2 1 0 22 2 0 6 4 2 0 6 4 2 0

23 3 1 7 5 3 1 7 5 3 1

Instruction Address Dummy Data 1 Data 2

CS#

SCK

IO0

IO1

IO2

IO3

Phase

7 6 5 4 3 2 1 0 20 4 0 4 4 0 4 0 4 0 4 0

21 5 1 5 5 1 5 1 5 1 5 1

22 6 2 6 6 2 6 2 6 2 6 2

23 7 3 7 7 3 7 3 7 3 7 3

Instruction Address Mode Dummy D1 D2 D3 D4

Document Number: 002-00497 Rev. *E Page 16 of 90

S25FL116K, S25FL132K, S25FL164K

3.3 Interface States

This section describes the input and output signal levels as related to the SPI interface behavior.

Legend:

Z = no driver - floating signal

HL = Host driving V

HH = Host driving V

HV = either HL or HH

X = HL or HH or Z

HT = toggling between HL and HH

ML = Memory driving V

MH = Memory driving V

MV = either ML or MH

3.3.1 Low Power Hardware Data Protection

When V

is less than V

the memory device will ignore commands to ensure that program and erase operations can not start

when the core supply voltage is out of the operating range.

3.3.2 Power-On (Cold) Reset

When the core voltage supply remains at or below the V

CC (Low)

voltage for > t

time, then rises

≥ V

the device will begin its Power-On-Reset (POR) process. POR continues until the end of t

PUW

. During t

PUW

the device does

not react to write commands. Following the end of t

PUW

the device transitions to the Interface Standby state and can accept write

commands. For additional information on POR see Power-On (Cold) Reset on page 25.

Table 3.1 Interface States Summary

Interface State V

SCK CS#

HOLD# /

IO3

WP# /

IO2

SO /

IO1

SI / IO0

Low Power

Hardware Data Protection

< V

XXXXZX

Power-On (Cold) Reset ≥ V

(min) X HH X X Z X

Interface Standby ≥ V

(min) X X X X Z X

Instruction Cycle ≥ V

(min) HT HL HH HV Z HV

Hold Cycle ≥ V

(min) HV or HT HL HL X X X

Single Input Cycle

Host to Memory Transfer

≥ V

(min) HT HL HH X Z HV

Single Latency (Dummy) Cycle ≥ V

(min) HT HL HH X Z X

Single Output Cycle

Memory to Host Transfer

≥ V

(min) HT HL HH X MV X

Dual Input Cycle

Host to Memory Transfer

≥ V

(min) HT HL HH X HV HV

Dual Latency (Dummy) Cycle ≥ V

(min) HT HL HH X X X

Dual Output Cycle

Memory to Host Transfer

≥ V

(min) HT HL HH X MV MV

Quad Input Cycle

Host to Memory Transfer

≥ V

(min) HT HL HV HV HV HV

Quad Latency (Dummy) Cycle ≥ V

(min) HT HL X X X X

Quad Output Cycle

Memory to Host Transfer

≥ V

(min) HT HL MV MV MV MV

Document Number: 002-00497 Rev. *E Page 17 of 90

S25FL116K, S25FL132K, S25FL164K

3.3.3 Interface Standby

When CS# is high the SPI interface is in standby state. Inputs are ignored. The interface waits for the beginning of a new command.

The next interface state is Instruction Cycle when CS# goes low to begin a new command.

While in interface standby state the memory device draws standby current (I

) if no embedded algorithm is in progress. If an

embedded algorithm is in progress, the related current is drawn until the end of the algorithm when the entire device returns to

standby current draw.

3.3.4 Instruction Cycle

When the host drives the MSB of an instruction and CS# goes low, on the next rising edge of SCK the device captures the MSB of

the instruction that begins the new command. On each following rising edge of SCK the device captures the next lower significance

bit of the 8-bit instruction. The host keeps CS# low, HOLD# high, and drives Write Protect (WP#) signal as needed for the

instruction. However, WP# is only relevant during instruction cycles of a Write Status Registers command and is otherwise ignored.

Each instruction selects the address space that is operated on and the transfer format used during the remainder of the command.

The transfer format may be Single, Dual output, Quad output, Dual I/O, or Quad I/O. The expected next interface state depends on

the instruction received.

Some commands are stand alone, needing no address or data transfer to or from the memory. The host returns CS# high after the

rising edge of SCK for the eighth bit of the instruction in such commands. The next interface state in this case is Interface Standby.

3.3.5 Hold

When Quad mode is not enabled (SR2[1]=0) the HOLD# / IO3 signal is used as the HOLD# input. The host keeps HOLD# low, SCK

may be at a valid level or continue toggling, and CS# is low. When HOLD# is low a command is paused, as though SCK were held

low. SI / IO0 and SO / IO1 ignore the input level when acting as inputs and are high impedance when acting as outputs during hold

state. Whether these signals are input or output depends on the command and the point in the command sequence when HOLD# is

asserted low.

When HOLD# returns high the next state is the same state the interface was in just before HOLD# was asserted low.

3.3.6 Single Input Cycle — Host to Memory Transfer

Several commands transfer information after the instruction on the single serial input (SI) signal from host to the memory device. The

dual output, and quad output commands send address to the memory using only SI but return read data using the I/O signals. The

host keeps CS# low, HOLD# high, and drives SI as needed for the command. The memory does not drive the Serial Output (SO)

signal.

The expected next interface state depends on the instruction. Some instructions continue sending address or data to the memory

using additional Single Input Cycles. Others may transition to Single Latency, or directly to Single, Dual, or Quad Output.

3.3.7 Single Latency (Dummy) Cycle

Read commands may have zero to several latency cycles during which read data is read from the main flash memory array before

transfer to the host. The number of latency cycles are determined by the instruction. During the latency cycles, the host keeps CS#

low, and HOLD# high. The Write Protect (WP#) signal is ignored. The host may drive the SI signal during these cycles or the host

may leave SI floating. The memory does not use any data driven on SI / I/O0 or other I/O signals during the latency cycles. In dual or

quad read commands, the host must stop driving the I/O signals on the falling edge at the end of the last latency cycle. It is

recommended that the host stop driving I/O signals during latency cycles so that there is sufficient time for the host drivers to turn off

before the memory begins to drive at the end of the latency cycles. This prevents driver conflict between host and memory when the

signal direction changes. The memory does not drive the Serial Output (SO) or I/O signals during the latency cycles.

The next interface state depends on the command structure i.e. the number of latency cycles, and whether the read is single, dual,

or quad width.

Document Number: 002-00497 Rev. *E Page 18 of 90

S25FL116K, S25FL132K, S25FL164K

3.3.8 Single Output Cycle — Memory to Host Transfer

Several commands transfer information back to the host on the single Serial Output (SO) signal. The host keeps CS# low, and

HOLD# high. The Write Protect (WP#) signal is ignored. The memory ignores the Serial Input (SI) signal. The memory drives SO

with data.

The next interface state continues to be Single Output Cycle until the host returns CS# to high ending the command.

3.3.9 Dual Input Cycle — Host to Memory Transfer

The Read Dual I/O command transfers two address or mode bits to the memory in each cycle. The host keeps CS# low, HOLD#

high. The Write Protect (WP#) signal is ignored. The host drives address on SI / IO0 and SO / IO1.

The next interface state following the delivery of address and mode bits is a Dual Latency Cycle if there are latency cycles needed or

Dual Output Cycle if no latency is required.

3.3.10 Dual Latency (Dummy) Cycle

Read commands may have zero to several latency cycles during which read data is read from the main flash memory array before

transfer to the host. The number of latency cycles are determined by the instruction. During the latency cycles, the host keeps CS#

low, and HOLD# high. The Write Protect (WP#) signal is ignored. The host may drive the SI / IO0 and SO / IO1 signals during these

cycles or the host may leave

SI / IO0 and SO / IO1 floating. The memory does not use any data driven on SI / IO0 and SO / IO1 during the latency cycles. The

host must stop driving SI / IO0 and SO / IO1 on the falling edge at the end of the last latency cycle. It is recommended that the host

stop driving them during all latency cycles so that there is sufficient time for the host drivers to turn off before the memory begins to

drive at the end of the latency cycles. This prevents driver conflict between host and memory when the signal direction changes. The

memory does not drive the SI / IO0 and SO / IO1 signals during the latency cycles.

The next interface state following the last latency cycle is a Dual Output Cycle.

3.3.11 Dual Output Cycle — Memory to Host Transfer

The Read Dual Output and Read Dual I/O return data to the host two bits in each cycle. The host keeps CS# low, and HOLD# high.

The Write Protect (WP#) signal is ignored. The memory drives data on the SI / IO0 and SO / IO1 signals during the dual output

cycles.

The next interface state continues to be Dual Output Cycle until the host returns CS# to high ending the command.

3.3.12 Quad Input Cycle — Host to Memory Transfer

The Read Quad I/O command transfers four address, mode, or data bits to the memory in each cycle. The host keeps CS# low, and

drives the IO signals.

For Read Quad I/O the next interface state following the delivery of address and mode bits is a Quad Latency Cycle if there are

latency cycles needed or Quad Output Cycle if no latency is required.

3.3.13 Quad Latency (Dummy) Cycle

Read commands may have zero to several latency cycles during which read data is read from the main flash memory array before

transfer to the host. The number of latency cycles are determined by the Latency Control in the Status Register-3 (SR3[3:0]). During

the latency cycles, the host keeps CS# low. The host may drive the IO signals during these cycles or the host may leave the IO

floating. The memory does not use any data driven on IO during the latency cycles. The host must stop driving the IO signals on the

falling edge at the end of the last latency cycle. It is recommended that the host stop driving them during all latency cycles so that

there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. This prevents

driver conflict between host and memory when the signal direction changes. The memory does not drive the IO signals during the

latency cycles.

The next interface state following the last latency cycle is a Quad Output Cycle.

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