嵌入式多处理器系统芯片软件设计与编程实践

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嵌入式软件设计与多处理器系统级芯片编程是当前信息技术领域的重要课题，特别是在随着物联网、工业4.0和自动化技术的发展中，嵌入式系统扮演着关键角色。本文档《嵌入式软件设计与多处理器系统级芯片编程》由Katalin Popovici、Frédéric Rousseau、Ahmed A. Jerraya和Marilyn Wolf共同编著，他们分别来自MathWorks, Inc.、Laboratoire TIMA（法国格勒诺布尔）和Tensilica Inc.等知名机构。嵌入式系统系列编辑由Nikil D. Dutt、Donald Bren等人负责，展示了这一领域的深度研究，该系列旨在探讨在复杂硬件环境中如何设计和实现高效的软件解决方案。本书特别关注了多处理器系统-on-chip (MPSoC)的设计，这种硬件架构集成了多个处理器核心在同一芯片上，为实时性和性能优化提供了可能。书中通过Simulink和SystemC的案例研究，深入剖析了如何利用这些工具进行软件设计和编程。Simulink是一种功能强大的动态模型构建工具，适用于系统仿真和控制系统的开发，而SystemC则是一个基于C语言的框架，特别适合于高性能实时系统的设计。作者们结合理论与实践，向读者展示了如何有效地整合和管理不同处理器间的通信，以及如何优化代码以充分利用MPSoC的并行特性。此外，本书还强调了软件设计中的模块化、可扩展性和安全性，这对于保证嵌入式系统的可靠性和长期维护至关重要。通过阅读这本书，读者不仅能掌握嵌入式软件的基础知识，还能了解到如何在实际项目中应用现代设计方法和工具，以应对日益增长的性能需求和复杂性挑战。《嵌入式软件设计与多处理器系统级芯片编程》是一本极具实用价值的参考资料，无论是初学者还是经验丰富的工程师，都能从中受益匪浅，提升他们在嵌入式系统开发领域的专业技能。

List of Tables

2.1 The six programming levels deﬁned by Skillicorn . . ........ 54

2.2 Additional models for SoC design . .................. 56

2.3 Programming model API at different abstraction levels ........ 57

2.4 SoftwarecommunicationAPIs .................... 89

2.5 SamplesoftwareIPlibrary....................... 91

4.1 Task code generation for motion JPEG . . . ............. 140

4.2 Messages through the AMBA bus . .................. 142

4.3 Task code generation for H.264 encoder . . . ............. 144

4.4 Results captured in Hermes NoC using DXM as

communication scheme . ....................... 147

5.1 Memory accesses ........................... 171

5.2 Mesh NoC routing requests ...................... 175

5.3 Torus NoC routing requests ...................... 177

5.4 Torus NoC amount of transmitted data (bytes) ............ 177

5.5 Execution and simulation times of the H.264 encoder for

different interconnect, communication, and IP mappings . . . .... 179

6.1 ARM7andARM9processorsfamily ................. 197

Chapter 1

Embedded Systems Design: Hardware

and Software Interaction

Abstract This chapter introduces the deﬁnitions of the basic concepts used in

the book. The chapter details the software and hardware organization for the het-

erogeneous MPSoC architectures and summarizes the main steps in programming

MPSoC. The software design represents an incremental process performed at four

MPSoC abstraction levels (system architecture, virtual architecture, transaction-

accurate architecture, and virtual prototype). At each design step, different software

components are generated and veriﬁed using hardware simulation models. The

overall design ﬂow is given in this chapter. Examples of target architectures and

applications, which will be used in the remaining part of this book, are described.

1.1 Introduction

Modern system-on-chip (SoC) design shows a clear trend toward integration

of multiple processor cores. Current embedded applications are migrating from

single processor-based systems to intensive data communication requiring multi-

processing systems. The performance demanded by these applications requires the

use of multi-processor architectures in a single chip (MPSoCs), endowed with

complex communication infrastructures, such as hierarchical buses or networks on

chips (NoCs). Additionally, heterogeneous cores are exploited to meet the tight

performance and design cost constraints. This trend of building heterogeneous

multi-processor SoC will be even accelerated due to current embedded application

requirements. As illustrated in Fig. 1.1, the survey conducted by Embedded Systems

Design Journal already proves that more than 50% of multi-processor architectures

are heterogeneous, integrating different types of processors [159].

In fact, the literature relates mainly two kinds of organizations for multi-

processor architectures. These are called shared memory and message passing

[42]. This classiﬁcation ﬁxes both hardware and software organizations for each

class. The shared memory organization generally assumes a multi-tasking appli-

cation organized as a single software stack, and a hardware architecture made

of several identical processors (CPUs), also called homogeneous symmetrical

K. Popovici et al., Embedded Software Design and Programming of Multiprocessor

System-on-Chip, Embedded Systems, DOI 10.1007/978-1-4419-5567-8_1,



Springer Science+Business Media, LLC 2010

2 1 Embedded Systems Design

Multiple identical CPUs

Multiple different CPUs

Single chip, same CPUs

Single chip, different CPUs

20%

40%

60%

Fig. 1.1 Types of processors in SoC

multi-processing (SMP) architecture. The communication between the different

CPUs is made through global shared memory. The message-passing organization

assumes in most cases multiple software stacks which may run either on an SMP

architecture or on non-identical processing subsystems, which may include different

CPUs and/or different I/O systems, in addition to speciﬁc local memory archi-

tecture. The communication between the different subsystems is generally made

through message passing. Heterogeneous MPSoCs generally combine both models,

and integrate a massive number of processors on a single chip [122]. Future het-

erogeneous MPSoC will be made of few heterogeneous subsystems, where each

subsystem includes a massive number of the same processor to run a speciﬁc

software stack [87].

Nowadays multimedia and telecom applications such as MPEG 2/4, H.263/4,

CDMA 2000, WCDMA, and MP3 contain heterogeneous functions that require dif-

ferent kinds of processing units (digital signal processor, shortly DSP, for complex

computation, microcontroller for control functions, etc.) and different communica-

tion schemes (fast links, non-standard memory organization, and access). To achieve

the required computation and communication performances, heterogeneous MPSoC

architecture with speciﬁc communication components seems to be a promising solu-

tion [101]. Heterogeneous MPSoC includes different kinds of processors (DSP,

microcontroller, ASIP, etc.) and different communication schemes. This type of

heterogeneous architecture provides highly concurrent computation and ﬂexible

programmability.

Typical heterogeneous platforms already used in industry are TI OMAP [156]

and ST Nomadik [114] for cellular phones, Philips Viper Nexperia [113] for con-

sumer products, or the Atmel Diopsis D940 architecture [44]. They incorporate a

DSP processor and a microcontroller, communicating via efﬁcient, but sophisticated

infrastructure.

1.1 Introduction 3

The evolution of cell phones is a good illustration of the evolution and het-

erogeneity of MPSoCs. Modern cell phones may have four to eight processors,

including one or more RISC processors for user interfaces, protocol stack pro-

cessing, and other control functions; a DSP for video encoding and decoding and

radio interface; an audio processor for music playback; a picture processor for cam-

era options; and even a video processor for new video-on-phone capabilities. In

addition, there may be other deeply embedded processors substituting for other

functions traditionally designed as hardware blocks [96]. Extensible processors

are proving to be ﬂexible substitutes for hardware blocks, achieving acceptable

performance and power consumption. Thus, these devices are a good example of

heterogeneous MPSoC, and their demanding requirements for low cost, reasonable

performance, and minimal energy consumption illustrate the advantages of using

highly application-speciﬁc processors for various functions.

Heterogeneous MPSoC architectures may be represented as a set of software

and hardware processing subsystems which interact via a communication network

(Fig. 1.2) [42].

Fig. 1.2 MPSoC hardware–software architecture

A software subsystem is a programmable subsystem, namely, a processor sub-

system. This integrates different hardware components including a processing unit

for computation (CPU), speciﬁc local components such as local memory, data and

control registers, hardware accelerators, interrupt controller, DMA engine, synchro-

nization components such as mailbox or semaphores, and speciﬁc I/O components

or other peripherals.

Each processor subsystem executes a speciﬁc software stack organized in two

main layers: the application and the hardware-dependent software (HdS) layers. The

application layer is associated with the high-level behavior of the heterogeneous

functions composing the target application. The HdS layer is associated with the

hardware-dependent low-level software behavior, such as interrupt service routines,

context switch, speciﬁc I/O control, and tasks scheduling. In fact, the HdS layer

includes three components: operating system (OS), speciﬁc I/O communication

4 1 Embedded Systems Design

(Comm), and the hardware abstraction layer (HAL). These different components

are based on well-deﬁned primitives or application programming interfaces (APIs)

in order to pass from one software layer to another.

A hardware subsystem represents speciﬁc hardware component that implements

speciﬁc functionalities of the application or a global memory subsystem accessible

by the processing units.

The shift from the single processor to an increasingly processor- and multi-

processor-centric design style poses many challenges for system architects, software

and hardware designers, veriﬁcation specialists, and system integrators. The main

design challenges for MPSoC are as follows: programming models that are required

to map application software into effective implementations, the synchronization

and control of multiple concurrent tasks on multiple processor cores, debugging

across multiple models of computation of MPSoC and the interaction between the

system, applications, and the software views, and the processor conﬁguration and

extension [96].

Current ASIC design approaches are hard to scale to a highly parallel multi-

processor SoC [88]. Designing these new systems by means of classical methods

gives unacceptable realization costs and delays. This is mainly because different

teams contributing to SoC design used to work separately. Traditional ASIC design-

ers have a hardware-centric view of the system design problem. Similarly, software

designers have a software-centric view. System-on-chip designs require the creation

and use of radical new design methodologies because some of the key problems in

SoC design lie at the boundary between hardware and software. Current SoC design

process uses in most cases two separate teams working in a serial methodology to

achieve hardware and software designs, while some SoC designers already adopted

a process involving mixed hardware–software teams, and others try to move slowly

in this direction.

The use of heterogeneous ASIPs makes heterogeneous MPSoC architectures fun-

damentally different from classic general-purpose multi-processor architectures. For

the design of classic computers, the parallel programming concept (e.g., MPI) is

used as an application programming interface (API) to abstract hardware/software

interfaces during high-level speciﬁcation of software applications. The application

software can be simulated using an execution platform of the API (e.g., MPICH) or

executed on existing multi-processor architectures that include a low-level software

layer to implement the programming model. In this case, the overall performances

obtained after hardware/software integration cannot be guaranteed and will depend

on the match between the application and the platform.

Unlike classic computers, the design of MPSoC requires a better matching

between hardware and software in order to meet performance requirements. In this

case, the hardware/software interfaces implementation is not standard; it needs to be

customized for a speciﬁc application in order to get the required performances. This

includes customizing the CPUs and all the peripherals required to accelerate com-

munication and computation. In most cases, even the lower software layers need to

be customized to reach the required cost and performance constraints. Applying

the classical design schemes for those architectures leads to inefﬁcient designs.

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