Spartan-6 FPGA DDR内存控制器MCB用户手册v2.3详解

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本篇文档是Spartan-6 FPGA Memory Controller User Guide (UG388)，版本为v2.3，发布日期为2010年8月9日。这份指南主要针对的是Spartan-6系列FPGA中的内存控制器（MCB），它专为与Xilinx硬件设备协同工作的设计开发而编写。Xilinx明确指出，这份文档仅限于在设计过程中使用，用户未经书面许可不得复制、分发、出版、下载、展示或通过任何形式，包括电子、机械、影印、录音等进行传播，除非用于与Xilinx硬件产品的特定开发。文档的使用受到严格限制，用户必须获得Xilinx的书面同意。Xilinx不对文档内容的正确性、完整性或适用性做出任何保证，也不承担因使用文档产生的任何责任。此外，Xilinx保留在不通知用户的情况下随时修改文档的权利，并且不对可能提供的技术支持或协助承担责任，这些服务仅限于文档所包含的信息。文档的发布是“按现状”提供，没有任何形式的质保，意味着用户应自行评估其在具体项目中的适用性和风险。因此，读者在使用Spartan-6 FPGA Memory Controller时，需要仔细阅读并理解文档中的各项指导，确保遵循最佳实践和官方建议，以避免潜在的设计问题或性能限制。主要内容涵盖了Spartan-6 FPGA的内存控制器功能、接口规范、配置步骤、常见问题解决方案以及性能优化技巧。深入学习该文档，设计师可以了解如何有效利用DDR（Double Data Rate）技术来提高系统带宽和数据传输速率，同时处理好内存访问的同步和异步模式，以及控制信号的时序和电源管理。对于高级FPGA用户和系统集成者来说，这份文档是理解和实现高性能、低功耗系统设计的关键参考资料。

Spartan-6 FPGA Memory Controller www.xilinx.com 11

UG388 (v2.3) August 9, 2010

Block Diagram

The single data rate (SDR) user interface to the MCB inside the FPGA can be configured for

one to six ports, with each port consisting of a command interface and a read and/or write

data interface. The two 32-bit bidirectional and four 32-bit unidirectional hardware-based

ports inside the MCB can be grouped to create five different port configurations.

Other major components of the MCB include:

•Arbiter

Determines which port currently has priority for accessing the memory device.

• Controller

Primary control block that converts the simple requests made at the user interface into

the necessary instructions and sequences required to communicate with the memory.

• Datapath

Handles the flow of write and read data between the memory device and the user

logic.

• Physical Interface (PHY)

Converts the controller instructions into the actual timing relationships and DDR

signaling necessary to communicate with the memory device.

• Calibration Logic

Calibrates the PHY for optimal performance and reliability.

X-Ref Target - Figure 1-1

Figure 1-1: Spartan-6 FPGA Memory Controller Block (IP Wrapper View)

UG388_c1_01_050409

32-Bit

Bidirectional

Arbiter

PHY

IOB

Datapath

IP Wrapper

Spartan-6 FPGA

Memory

Controller

Calibration

Logic

DDR

DDR2

DDR3

LPDDR

32-Bit

Bidirectional

32-Bit

Unidirectional

32-Bit

Unidirectional

32-Bit

Unidirectional

32-Bit

Unidirectional

CMD FIFO 0

CMD FIFO 1

CMD FIFO 2

CMD FIFO 3

CMD FIFO 4

CMD FIFO 5

User Logic

Dedicated Routing

I/O Clocking Network

12 www.xilinx.com Spartan-6 FPGA Memory Controller

UG388 (v2.3) August 9, 2010

Chapter 1: Memory Controller Block Overview

Performance

The dedicated MCB cores in Spartan-6 devices enable significantly higher performance

levels than equivalent IP solutions implemented in the FPGA logic. Because memory

bandwidth is often the bottleneck in overall system performance, the MCB cores were

specifically engineered for users looking to maximize memory performance in a low-cost,

low-power FPGA device.

Each MCB core supports the memory interface data rates and total memory bandwidth

specifications shown in Table 1-1. Peak bandwidth for a single MCB memory interface is

calculated for the three supported interface widths.

Note:

The MCB supports Standard and Extended performance modes depending on the selected

CCINT

operating conditions. Peak data rates shown in Tabl e 1- 1 represent maximum performance

when using the V

CCINT

range in Extended performance mode. Refer to Table 2 (Recommended

Operating Conditions) and the Performance Characteristics section in DS162, Spartan-6 FPGA Data

Sheet: DC and Switching Characteristics for V

CCINT

operating conditions and performance

specifications for Standard and Extended modes.

Table 1-1: Memory Interface Data Rates and Peak Bandwidth for Each MCB

Memory Type

Data Rate:

Mb/s DDR (MHz Clock)

Peak Bandwidth per MCB Interface (Gb/s)

Minimum Maximum

(1)

4-Bit 8-Bit 16-Bit

DDR 167 Mb/s

(2)

(83.3 MHz)

400 Mb/s

(200 MHz)

1.6Gb/s 3.2Gb/s 6.4Gb/s

DDR2 250 Mb/s

(2)

(125 MHz)

800 Mb/s

(400 MHz)

3.2 Gb/s 6.4 Gb/s 12.8 Gb/s

DDR3 606 Mb/s

(2)

(303 MHz)

800 Mb/s

(400 MHz)

3.2 Gb/s 6.4 Gb/s 12.8 Gb/s

LPDDR 60 Mb/s

(2)

(30 MHz)

400 Mb/s

(200 MHz)

1.6Gb/s 3.2Gb/s 6.4Gb/s

Notes:

1. The maximum MCB data rate shown does not apply to all speed grades. Refer to DS162, Spartan-6

FPGA Data Sheet: DC and Switching Characteristics, for performance by speed grade. The

-3N speed-grade devices do not support the MCB.

2. The minimum frequency requirement of the MCB is dictated by the minimum frequency specification

for the memory standard. See Memory Standards in Appendix A for links to the relevant JEDEC

specifications.

14 www.xilinx.com Spartan-6 FPGA Memory Controller

UG388 (v2.3) August 9, 2010

Chapter 1: Memory Controller Block Overview

Supported Memory Configurations

The Spartan-6 FPGA MCB supports a wide range of common memory types,

configurations, and densities, as shown in Table 1-3.

Software and Tool Support

The Spartan-6 FPGA MCB is supported by standard software and tool flows like other soft

and embedded IP blocks offered by Xilinx. For conventional (i.e., non-embedded) FPGA

designs, the MCB can be integrated into a design using the Memory Interface Generator

(MIG) tool, available in the CORE Generator tool.

The MIG tool is used to generate memory interfaces for all Xilinx FPGAs. It produces the

necessary RTL design files, user constraints files (UCFs), and script files for simulation and

implementation of memory solutions offered by Xilinx. The Getting Started chapter in

UG416

, Spartan-6 FPGA Memory Interface Solutions User Guide, contains detailed

step-by-step instructions on how to use the MIG tool to implement memory interfaces

based on the MCB.

For embedded designs (e.g., MicroBlaze™ processor designs), the IP configurator GUI

found in the Xilinx Platform Studio tool within the EDK environment can be used to

specify the memory interface characteristics. In this flow, the MCB serves as the underlying

hardware implementation of the MPMC IP block, available in the EDK library. In addition

to setting up the controller and memory attributes, the tool generates the necessary soft

bridges to the PLB bus, Xilinx Cache Link (XCL), LocalLink (LL), or other specified

interface for connecting EDK peripherals to the resulting memory controller ports.

Table 1-3: Supported Memory Configurations

Memory Density

Width

(# DQ bits)

Memory Type

LPDDR DDR DDR2 DDR3

128 Mb x16 X X

x8 X

x4 X

256 Mb x16 X X X

x8 X X

x4 X X

512Mbx16XXXX

x8 XXX

x4 XXX

1 Gbx16XXXX

x8 XXX

x4 XXX

2 Gb x16 X X

x8 X X

x4 X X

4 Gb

(1)

x16 X

Notes:

1. The MCB supports single-die, 4 Gb memory components (when available from memory suppliers) but

not dual-die, 4 Gb memory components.

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