FPGA设计专家：解决集成挑战与推荐学习资源

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FPGA（Field-Programmable Gate Array）技术是现代电子设计的关键领域，它允许设计师在硬件级别进行定制化编程，灵活且高效。"FPGAs: World Class Designs"这个主题涵盖了从电路综合中的挑战到高级设计策略的深入探讨。在设计过程中，遇到警告和性能优化的问题是常见的，这涉及到如何遵循同步设计原则，决定是追求速度优势还是面积效率，以及构建有效的时钟树来管理异步信号同步。时钟树设计至关重要，因为它能确保系统中的各个部分以精确的时间同步工作。推荐的学习资源包括《FPGA权威指南》，该书全面介绍了FPGA的基础概念和技术；《IP核芯志-数字逻辑设计思想》则深入讲解了IP内核的设计思想，帮助理解核心组件的构建；《Altera FPGA/CPLD设计》第二版则分别提供了基础篇和高级篇，从入门到进阶，逐步提升读者的设计技能。 Maxfield，作为一位电子和计算机领域的专家，拥有控制工程学士学位，他的职业生涯中涵盖了广泛的电子产品设计领域，从ASIC（Application-Specific Integrated Circuit）设计到PCB（Printed Circuit Board）制作，甚至涉足电子设计自动化（EDA）的多个层面。他目前担任TechBites Interactive的总裁，这家公司专注于将技术产品的价值传递给非技术人员，通过多种媒介如网站、广告、技术文档、宣传材料等进行有效沟通。 Max不仅在国际杂志和会议上发表众多技术文章，还亲自撰写了书籍，这表明他在FPGA设计方面的知识不仅限于理论，而是结合实战经验和实践技巧，为学习者提供了丰富的学习资料。通过阅读这些教材和参考Max的作品，设计师可以掌握如何有效地解决FPGA设计中的问题，并在实践中提升自己的世界一流的FPGA设计能力。

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MORE ON PROGRAMMING TECHNOLOGIES

SRAM-based Devices

As seen in Chapter 1, the majority of FPGAs are based on the use of SRAM

configuration cells, which means that they can be configured over and over

again. The main advantages of this programming technology are that new

design ideas can be quickly implemented and tested, while evolving standards

and protocols can be accommodated relatively easily. Furthermore, when the

system is first powered up, the FPGA can initially be programmed to perform

one function such as a self-test or board/system test, and it can then be repro-

grammed to perform its main task.

Another big advantage of the SRAM-based approach is that these devices

are at the forefront of technology. FPGA vendors can leverage the fact that many

other companies specializing in memory devices expend tremendous resources

on research and development (R & D) in this area. Furthermore, the SRAM cells

are created using exactly the same CMOS technologies as the rest of the device,

so no special processing steps are required in order to create these components.

Unfortunately, there’s no such thing as a free lunch. One downside of SRAM-

based devices is that they have to be reconfigured every time the system is pow-

ered up. This either requires the use of a special external memory device (which

has an associated cost and consumes real estate on the board) or of an on-board

microprocessor (or some variation of these techniques—see also Chapter 3).

that their smallest structures were 3 millionths of a meter in size. Now, devices

at 0.09 μ m have appeared.

● Any geometry smaller than around 0.5 μ m is referred to as deep submicron

(DSM) . At some point that is not well deﬁ ned (or that has multiple deﬁ nitions

depending on whom one is talking to), we move into the ultradeep submicron

(UDSM) realm.

● We’ll also discuss the important topic of intellectual property (IP) in this chap-

ter. This term refers to functional design blocks that have already been devel-

oped and can be purchased to put into an IC design. IP blocks can range all the

way up to sophisticated communications functions and microprocessors. The

more complex functions, like microprocessors, may be referred to as “ cores. ”

Insider Info

When geometries dropped below 1 μ m, things became a little awkward, not the

least because it’s a pain to keep saying things like “ zero point one three microns. ”

For this reason, when conversing it’s becoming common to talk in terms of nano,

where one nano (short for nanometer) equates to a thousandth of a micron.

Instead of mumbling “ point zero nine microns ” (0.09 μ m), one can simply

proclaim “ ninety nano ” (90 nano) and have done with it.

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Chapter | 2 FPGA Architectures

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On the bright side, some of today’s SRAM-based FPGAs support the

concept of bitstream encryption . In this case, the final configuration data is

encrypted before being stored in the external memory device. The encryption

key itself is loaded into a special SRAM-based register in the FPGA via its

JTAG port (see also Chapter 3). In conjunction with some associated logic, this

key allows the incoming encrypted configuration bitstream to be decrypted as

it’s being loaded into the device.

The command/process of loading an encrypted bitstream automatically dis-

ables the FPGA’s read-back capability. This means that you will typically use

unencrypted configuration data during development (where you need to use

read-back) and then start to use encrypted data when you move into produc-

tion. (You can load an unencrypted bitstream at any time, so you can easily

load a test configuration and then reload the encrypted version.)

—Technology Trade-offs—

● The main downside to the encrypted bitstream scheme is that you require a

battery backup on the circuit board to maintain the contents of the encryp-

tion key register in the FPGA when power is removed from the system.

This battery will have a lifetime of years or decades because it need only

maintain a single register in the device, but it does add to the size, weight,

complexity, and cost of the board.

ALERT!

Remember that there are reverse-engineering companies all over the world special-

izing in the recovery of “ design IP. ” And there are also a number of countries whose

governments turn a blind eye to IP theft so long as the money keeps rolling in (you

know who you are). So if a design is a high-profit item, you can bet that there are

folks out there who are ready and eager to replicate it while you’re not looking.

In reality, the real issue here is not related to those stealing your IP by

reverse-engineering the contents of the configuration file, but rather their abil-

ity to clone your design, irrespective of whether they understand how it works.

Using readily available technology, it is relatively easy for someone to take a cir-

cuit board, put it on a “ bed of nails ” tester, and quickly extract a complete netlist

for the board. This netlist can subsequently be used to reproduce the board. Now

the only task remaining for the nefarious scoundrels is to copy your FPGA con-

figuration file from its boot PROM (or EPROM, E2PROM, or whatever), and they

have a duplicate of the entire design.

Security Issues

Another consideration with regard to SRAM-based devices is that it can be

difficult to protect your intellectual property , or IP, in the form of your design.

This is because the configuration file used to program the device is stored in

some form of external memory.

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Antifuse-based Devices

Unlike SRAM-based devices, which are programmed while resident in the

system, antifuse-based devices are programmed off-line using a special device

programmer. The proponents of antifuse-based FPGAs are proud to point to an

assortment of (not-insignificant) advantages:

1. First, these devices are nonvolatile (their configuration data remains when

the system is powered down), which means that they are immediately

available as soon as power is applied to the system, and they don’t require

an external memory chip to store their configuration data, which saves the

cost of an additional component and saves real estate on the board.

2. Another noteworthy advantage of antifuse-based FPGAs is the fact that

their interconnect structure is naturally rad hard , which means they are

relatively immune to the effects of radiation. This is of particular interest in

the case of military and aerospace applications because the state of a con-

figuration cell in an SRAM-based component can be “ flipped ” if that cell

is hit by radiation (of which there is a lot in space). By comparison, once

an antifuse has been programmed, it cannot be altered in this way.

ALERT!

It should be noted that any flip-flops in these devices remain sensitive to radia-

tion, so chips intended for radiation-intensive environments must have their flip-

flops protected by triple redundancy design. This refers to having three copies of

each register and taking a majority vote (ideally all three registers will contain

identical values, but if one has been “ flipped ” such that two registers say 0 and

the third says 1, then the 0s have it, or vice versa if two registers say 1 and the

third says 0).

3. Perhaps the most significant advantage of antifuse-based FPGAs is that

their configuration data is buried deep inside them, making it almost

impossible to reverse-engineer the design . By default, it is possible for

the device programmer to read this data out because this is actually how

the programmer works. As each antifuse is being processed, the device pro-

grammer keeps on testing it to determine when that element has been fully

programmed; then it moves on to the next antifuse. Furthermore, the device

programmer can be used to automatically verify that the configuration was

performed successfully (this is well worth doing when you’re talking about

devices containing 50 million plus programmable elements). Once the

device has been programmed, however, it is possible to set (grow) a special

security antifuse that subsequently prevents any programming data (in the

form of the presence or absence of antifuses) from being read out of the

device. Even if the device is decapped (its top is removed), programmed

and unprogrammed antifuses appear to be identical, and the fact that all of

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Chapter | 2 FPGA Architectures

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the antifuses are buried in the internal metallization layers makes reverse-

engineering close to impossible.

Of course, the main disadvantage associated with antifuse-based devices is that

they are OTP, so once you’ve programmed one, its function is set in stone. This

makes these components a poor choice for use in a development or prototyp-

ing environment.

—Technology Trade-offs—

● Vendors of antifuse-based FPGAs may tout the fact that an antifuse-based

device consumes only 20 percent (approximately) of the standby power of an

equivalent SRAM-based component, that their operational power consumption

is also significantly lower, and that their interconnect-related delays are smaller.

Also, they might casually mention that an antifuse is much smaller and thus

occupies much less real estate on the chip than an equivalent SRAM cell.

● They may neglect to mention, however, that antifuse devices also require

extra programming circuitry, including a large, hairy programming transis-

tor for each antifuse.

● Also, antifuse technology requires the use of around three additional pro-

cess steps after the main manufacturing process has been qualified. For this

(and related) reason, antifuse devices are always at least one—and usually

several—generations (technology nodes) behind SRAM-based components,

which effectively wipes out any speed or power consumption advantages

that might otherwise be of interest.

PROM/FLASH-based Devices

PROM- or FLASH-based FPGAs are similar to their SRAM counterparts

in that their configuration cells are connected together in a long shift-register-

style chain. These devices can be configured off-line using a device program-

mer. Alternatively, some versions are in-system programmable, or ISP, but

their programming time is about three times that of an SRAM-based compo-

nent. However, they do have some advantages:

1. Once programmed, the data they contain is nonvolatile , so these devices

would be “ instant on ” when power is first applied to the system.

2. With regard to protection, some of these devices use the concept of a mul-

tibit key , which can range from around 50 bits to several hundred bits in

size. Once you’ve programmed the device, you can load your user-defined

key (bit-pattern) to secure its configuration data. After the key has been

loaded, the only way to read data out of the device, or to write new data

into it, is to load a copy of your key via the JTAG port (this port is dis-

cussed later in this chapter and in Chapter 3). The fact that the JTAG port

in today’s devices runs at around 20 MHz means that it would take billions

of years to crack the key by exhaustively trying every possible value.

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3. Two-transistor E

PROM and FLASH cells are approximately 2.5 times the

size of their one-transistor EPROM cousins, but they are still way smaller

than their SRAM counterparts . This means that the rest of the logic can

be much closer together, thereby reducing interconnect delays .

On the downside, these devices require around five additional process steps

on top of standard CMOS technology, which results in their lagging behind

SRAM-based devices by one or more generations (technology nodes). Last but

not least, these devices tend to have relatively high static power consumption

due to their containing vast numbers of internal pull-up resistors.

Hybrid FLASH-SRAM Devices

Last but not least, there’s always someone who wants to add yet one more

ingredient to the cooking pot. In the case of FPGAs, some vendors offer esoteric

combinations of programming technologies. For example, consider a device

where each configuration element is formed from the combination of a FLASH

(or E

PROM) cell and an associated SRAM cell.

In this case, the FLASH elements can be preprogrammed. Then, when the

system is powered up, the contents of the FLASH cells are copied in a mas-

sively parallel fashion into their corresponding SRAM cells. This technique

gives you the nonvolatility associated with antifuse devices, which means the

device is immediately available when power is first applied to the system. But

unlike an antifuse-based component, you can subsequently use the SRAM cells

to reconfigure the device while it remains resident in the system. Alternatively,

you can reconfigure the device using its FLASH cells either while it remains

in the system or off-line by means of a device programmer.

FINE-, MEDIUM-, AND COARSE-GRAINED ARCHITECTURES

It is common to categorize FPGA offerings as being either fine grained or

coarse grained. In order to understand what this means, we first need to remind

ourselves that the main feature that distinguishes FPGAs from other devices is

that their underlying fabric predominantly consists of large numbers of rela-

tively simple programmable logic block “ islands ” embedded in a “ sea ” of pro-

grammable interconnect ( Figure 2-1 ).

In the case of a fine-grained architecture , each logic block can be used to

implement only a very simple function. For example, it might be possible to con-

figure the block to act as any 3-input function, such as a primitive logic gate (AND,

OR, NAND, etc.) or a storage element (D-type flip-flop, D-type latch, etc.).

In the case of a coarse-grained architecture , each logic block contains a

relatively large amount of logic compared to their fine-grained counterparts.

For example, a logic block might contain four 4-input LUTs, four multiplex-

ers, four D-type flip-flops, and some fast carry logic (see the following topics

in this chapter for more details).

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