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FPGAs: Instant Access
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3. Two-transistor E
2
PROM and FLASH cells are approximately 2.5 times the
size of their one-transistor EPROM cousins, but they are still way smaller
than their SRAM counterparts . This means that the rest of the logic can
be much closer together, thereby reducing interconnect delays .
On the downside, these devices require around five additional process steps
on top of standard CMOS technology, which results in their lagging behind
SRAM-based devices by one or more generations (technology nodes). Last but
not least, these devices tend to have relatively high static power consumption
due to their containing vast numbers of internal pull-up resistors.
Hybrid FLASH-SRAM Devices
Last but not least, there’s always someone who wants to add yet one more
ingredient to the cooking pot. In the case of FPGAs, some vendors offer esoteric
combinations of programming technologies. For example, consider a device
where each configuration element is formed from the combination of a FLASH
(or E
2
PROM) cell and an associated SRAM cell.
In this case, the FLASH elements can be preprogrammed. Then, when the
system is powered up, the contents of the FLASH cells are copied in a mas-
sively parallel fashion into their corresponding SRAM cells. This technique
gives you the nonvolatility associated with antifuse devices, which means the
device is immediately available when power is first applied to the system. But
unlike an antifuse-based component, you can subsequently use the SRAM cells
to reconfigure the device while it remains resident in the system. Alternatively,
you can reconfigure the device using its FLASH cells either while it remains
in the system or off-line by means of a device programmer.
FINE-, MEDIUM-, AND COARSE-GRAINED ARCHITECTURES
It is common to categorize FPGA offerings as being either fine grained or
coarse grained. In order to understand what this means, we first need to remind
ourselves that the main feature that distinguishes FPGAs from other devices is
that their underlying fabric predominantly consists of large numbers of rela-
tively simple programmable logic block “ islands ” embedded in a “ sea ” of pro-
grammable interconnect ( Figure 2-1 ).
In the case of a fine-grained architecture , each logic block can be used to
implement only a very simple function. For example, it might be possible to con-
figure the block to act as any 3-input function, such as a primitive logic gate (AND,
OR, NAND, etc.) or a storage element (D-type flip-flop, D-type latch, etc.).
In the case of a coarse-grained architecture , each logic block contains a
relatively large amount of logic compared to their fine-grained counterparts.
For example, a logic block might contain four 4-input LUTs, four multiplex-
ers, four D-type flip-flops, and some fast carry logic (see the following topics
in this chapter for more details).
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