XC3S系列FPGA配置指南：UG332详解 Spartan-3A/E/F配置资料

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本资源是Xilinx针对XC3S系列FPGA（包括XC3S3200AN和XC3S50AN）的配置文档，即《Spartan-3 Generation Configuration User Guide》的第v1.4版，发布日期为2008年7月1日。这份用户指南主要介绍了Spartan-3A、Spartan-3E和Spartan-3FPGA家族的配置方法和流程。Xilinx通过此文档向用户揭示了设计细节和技术，旨在帮助开发者在其设计中有效地操作或与Xilinx FPGA进行接口。文档的核心内容涵盖了以下几个方面： 1. **概述**：文档首先明确了它适用于的硬件平台和版本，强调了用户在使用时必须遵守的版权和知识产权协议，指出未经授权的复制、分发或使用可能会触犯版权法、商标法、隐私权和公共宣传法以及通信法规。 2. **Spartan-3系列介绍**：文档详述了Spartan-3系列FPGA的不同型号，如Spartan-3A和Spartan-3E，这些FPGA具有各自的特性，可能会影响到配置策略的选择和优化。 3. **配置过程**：作为用户指南，它会详细阐述如何对这些FPGA进行配置，包括但不限于配置文件的创建、编程方法、配置模式的选择，以及可能涉及的专用工具和技术，例如JTAG接口或配置闪存。 4. **安全性和合规性**：Xilinx提醒用户在使用设计时需要注意保护知识产权，并且明确声明不承担因应用或使用设计而产生的任何责任，也不授予任何专利许可。 5. **访问资源**：文档提供了Xilinx的官方网站（www.xilinx.com），用户可以在此获取最新的技术支持、更新和相关技术文档。这份《Spartan-3 Generation Configuration User Guide》是工程师在设计和使用XC3S系列FPGA时的重要参考资料，它提供了全面的指导，确保用户在进行FPGA配置时遵循最佳实践，同时遵守严格的版权规定。无论是初次接触Xilinx FPGA的设计师还是经验丰富的专业人士，都需要深入了解并遵循这份文档中的内容，以实现高效和合规的开发工作。

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UG332 (v1.4) July 1, 2008

Figure 9-8: Configure Devices Using JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Figure 9-9: iMPACT Automatically Detects Devices on the JTAG Chain . . . . . . . . . . . 203

Figure 9-10: iMPACT Prompts for FPGA Bitstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Figure 9-11: iMPACT Automatically Adjusts FPGA Startup Clock

for JTAG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Figure 9-12: Click Bypass to Skip Platform Flash Programming . . . . . . . . . . . . . . . . . . . 205

Figure 9-13: Click Bypass to Skip CPLD Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Figure 9-14: Double-Click Program to Configure FPGA via JTAG . . . . . . . . . . . . . . . . . 206

Figure 9-15: FPGA Programming Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Chapter 10: Internal Master SPI Mode

Figure 10-1: Spartan-3AN FPGA using Internal Master SPI Flash Mode . . . . . . . . . . . . 209

Figure 10-2: Spartan-3AN SPI_ACCESS Design Primitive . . . . . . . . . . . . . . . . . . . . . . . . 211

Figure 10-3: Double-click Generate PROM, ACE or JTAG File . . . . . . . . . . . . . . . . . . . . 213

Figure 10-4: Prepare a PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Figure 10-5: Set Options for Spartan-3AN In-System Flash PROM. . . . . . . . . . . . . . . . . 215

Figure 10-6: Select a Spartan-3AN FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Figure 10-7: Specify the FPGA Configuration Bitstream(s) . . . . . . . . . . . . . . . . . . . . . . . . 217

Figure 10-8: Review Spartan-3AN In-System Memory Formatting Settings . . . . . . . . . 218

Figure 10-9: Add FPGA Configuration Bitstream File(s) . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 10-10: iMPACT View of the Spartan-3AN In-System Flash Memory. . . . . . . . . 219

Figure 10-11: Generate the Spartan-3AN In-System Flash File. . . . . . . . . . . . . . . . . . . . . 219

Chapter 11: Configuration Bitstream Generator (BitGen) Settings

Chapter 12: Sequence of Events

Figure 12-1: Spartan-3 Generation FPGA Configuration Process. . . . . . . . . . . . . . . . . . . 231

Figure 12-2: FPGA Wake from Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Figure 12-3: Spartan-3E/3A Reset Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Figure 12-4: FPGA Power-Up Timing Waveforms (Master Modes). . . . . . . . . . . . . . . . . 234

Figure 12-5: Clear Configuration Memory (Initialization). . . . . . . . . . . . . . . . . . . . . . . . . 235

Figure 12-6: Sample Control Pins (Mode Select, Variant Select) . . . . . . . . . . . . . . . . . . . 235

Figure 12-7: Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Figure 12-8: Check Array ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Figure 12-9: Load Configuration Data Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Figure 12-10: Cyclic Redundancy Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Figure 12-11: Startup Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Figure 12-12: Default Start-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Figure 12-13: Spartan-3E/3A FPGA Configuration Logic Conceptual Block Diagram . 244

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UG332 (v1.4) July 1, 2008

Chapter 13: Configuration-Related Design Primitives

Figure 13-1: BSCAN Primitive for Spartan-3A/3AN/3A DSP FPGAs . . . . . . . . . . . . . . . 245

Figure 13-2: STARTUP Primitive for Spartan-3E/3A FPGAs. . . . . . . . . . . . . . . . . . . . . . . 247

Figure 13-3: CAPTURE Primitive for Spartan-3A/3AN/3A DSP FPGAs . . . . . . . . . . . . . 248

Figure 13-4: ICAP Primitive (only available on Spartan-3A/3AN/3A DSP FPGAs) . . . 250

Figure 13-5: DNA_PORT Primitive (only available on Spartan-3A FPGAs) . . . . . . . . . 251

Chapter 14: Reconfiguration and MultiBoot

Figure 14-1: Example Spartan-3E MultiBoot Application using

1Mbyte Parallel Flash PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Figure 14-2: Prepare a MultiBoot PROM Image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Figure 14-3: Select a PROM Supporting MultiBoot for Spartan-3E FPGAs . . . . . . . . . . 257

Figure 14-4: Select the Configuration Direction of the First MultiBoot Image . . . . . . . 258

Figure 14-5: Select a PROM Size and Add It to the Design . . . . . . . . . . . . . . . . . . . . . . . . 258

Figure 14-6: Confirm the PROM Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

Figure 14-7: Select the First MultiBoot Configuration Image . . . . . . . . . . . . . . . . . . . . . . 259

Figure 14-8: Select the Second MultiBoot Configuration Image . . . . . . . . . . . . . . . . . . . 260

Figure 14-9: Generate the PROM File Using the Specified Parameters . . . . . . . . . . . . . 261

Figure 14-10: PROMGen Report File (*.prm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Figure 14-11: Spartan-3A MultiBoot Example using XC3S700A and SPI Flash . . . . . . 271

Figure 14-12: Prepare a MultiBoot PROM Image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Figure 14-13: Select a PROM Supporting MultiBoot for Spartan-3A FPGAs . . . . . . . . 272

Figure 14-14: SPI or Parallel Flash PROMs are Supported . . . . . . . . . . . . . . . . . . . . . . . . 273

Figure 14-15: Enter a PROM Density and Specify MultiBoot Image Start Locations. . 273

Figure 14-16: Confirm PROM Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Figure 14-17: Select the First (Default) Configuration Image . . . . . . . . . . . . . . . . . . . . . . 275

Figure 14-18: Select the Third MultiBoot Configuration Image . . . . . . . . . . . . . . . . . . . . 275

Figure 14-19: Generate the PROM File Using the Specified Parameters . . . . . . . . . . . . 276

Figure 14-20: Spartan-3A/3AN/3A DSP MultiBoot Configuration Mode Control . . . . 278

Chapter 15: Protecting FPGA Designs

Figure 15-1: Setting Bitstream Generator Options from ISE Project Navigator . . . . . . 281

Figure 15-2: Bitstream Generator Security Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

Figure 15-3: Spartan-3A/3AN/3A DSP DNA_PORT Design Primitive . . . . . . . . . . . . . . 284

Figure 15-4: DNA_PORT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

Figure 15-5: Possible Options for DIN Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Figure 15-6: Spartan-3A/3AN/3A DSP FPGA Configures Normally . . . . . . . . . . . . . . . . 288

Figure 15-7: Spartan-3A FPGA Authenticates PROM Image Against Device DNA. . . 288

Figure 15-8: Authentication Fails Using an Unauthorized Copy . . . . . . . . . . . . . . . . . . . 289

Figure 15-9: Spartan-3E FPGA Authentication Example using

Commodity Flash PROM with Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

Figure 15-10: Spartan-3E Authenticates PROM Image Against PROM’s Device ID . . 291

Figure 15-11: Intelligent Host Downloads a Spartan-3A Bitstream . . . . . . . . . . . . . . . . . 292

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UG332 (v1.4) July 1, 2008

Chapter 1: Overview and Design Considerations

Table 1-1: Spartan-3 Self-Loading Configuration Modes and Memory Sources . . . . . . . 27

Table 1-2: Spartan-3 Generation Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 1-3: PROM Families and Footprint Compatible Package Migration. . . . . . . . . . . . 34

Table 1-4: Number of Bits in an Uncompressed FPGA Bitstream Image . . . . . . . . . . . . . 36

Table 1-5: Spartan-3 Generation Configuration Data Frames . . . . . . . . . . . . . . . . . . . . . . . 37

Table 1-6: Maximum CCLK Frequency When Using Compressed Bitstream . . . . . . . . . 38

Table 1-7: Command Line to Review Bitstream Generator Options per Family . . . . . . . 43

Chapter 2: Configuration Pins and Behavior during Configuration

Table 2-1: Mode Pin Settings and Associated FPGA Configuration Mode by Family . . 46

Table 2-2: M[2:0] Mode Pin Differences between Spartan-3 Generation FPGAs . . . . . . 46

Table 2-3: Default Post-Configuration Behavior of M[2:0] Pin . . . . . . . . . . . . . . . . . . . . . . 48

Table 2-4: DriveDone Bitstream Generator Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 2-5: DonePin Bitstream Generator Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 2-6: Interaction between DriveDone and DonePin BitGen Options. . . . . . . . . . . . 50

Table 2-7: PROG_B Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 2-8: CCLK Differences between Spartan-3 Generation FPGA Families. . . . . . . . . 53

Table 2-9: Pins with Dedicated Pull-Up Resistors during Configuration

(All Spartan-3 Generation FPGAs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 2-10: Pins with Dedicated Pull-Up Resistors during Configuration

(Spartan-3A/3AN/3A DSP FPGA Family Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 2-11: Pins with Dedicated Pull-Up Resistors during Configuration

(Spartan-3 FPGA Family Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 2-12: Pull-Up Resistor during Configuration Control Input. . . . . . . . . . . . . . . . . . . 60

Table 2-13: Pull-Up Resistor Ranges by Spartan-3 Generation Family . . . . . . . . . . . . . . . 61

Table 2-14: Recommended External Pull-Up or Pull-down Resistor Values

to Define Input Values during Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 2-15: Spartan-3 Configuration Pins, Associated Modes, and Function. . . . . . . . . . 62

Table 2-16: Spartan-3A/3AN/3A DSP FPGAs: Pin Behavior during Configuration . . . . 66

Table 2-17: Spartan-3E FPGAs: Pin Behavior during Configuration . . . . . . . . . . . . . . . . . 67

Table 2-18: Pin Behavior during Configuration for Spartan-3 FPGA Family. . . . . . . . . . 68

Table 2-19: Default I/O Standard Setting During Configuration . . . . . . . . . . . . . . . . . . . . 68

Table 2-20: Supported Configuration Interface Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 2-21: Pull-up or Pull-down Values for HSWAP, M[2:0], and VS[2:0] . . . . . . . . . . . 71

Schedule of Tables

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UG332 (v1.4) July 1, 2008

Chapter 3: Master Serial Mode

Table 3-1: Spartan-3E/Spartan-3A/3A DSP FPGA Connections . . . . . . . . . . . . . . . . . . . . . 74

Table 3-2: Spartan-3 FPGA Connections to Platform Flash PROM . . . . . . . . . . . . . . . . . . 76

Table 3-3: Master Serial Configuration Mode Connections. . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 3-4: Number of Bits to Program a Spartan-3 Generation FPGA

and Smallest Platform Flash PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 3-5: Maximum ConfigRate Settings Using Platform Flash . . . . . . . . . . . . . . . . . . . . 80

Table 3-6: Xilinx Platform Flash Production Programmers . . . . . . . . . . . . . . . . . . . . . . . . . 93

Chapter 4: Master SPI Mode

Table 4-1: Master SPI Mode Support within Spartan-3 Generation FPGAs. . . . . . . . . . . 98

Table 4-2: SPI Flash Memory Devices Officially Supported by Xilinx

and Programmed Using iMPACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 4-3: SPI Serial Flash PROMs Supported by iMPACT . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 4-4: SPI Read Commands Supported by Spartan-3 Generation FPGAs. . . . . . . . 100

Table 4-5: Other SPI Flash Memory Devices With Data Sheet Compatibility . . . . . . . . 101

Table 4-6: Number of Bits to Program a Spartan-3E/3A and Smallest SPI Flash . . . . . . 102

Table 4-7: Example SPI Flash PROM Connections and Pin Naming. . . . . . . . . . . . . . . . 102

Table 4-8: Serial Peripheral Interface (SPI) Connections . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 4-9: Example Minimum Power-On to Select Times for Various SPI Flash . . . . . 106

Table 4-10: Spartan-3E/3A Power-On Reset Timing and Thresholds. . . . . . . . . . . . . . . . 108

Table 4-11: FPGA ConfigRate Setting and Corresponding SPI Flash PROM

Clock-to-Output Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 4-12: Summary of SPI Flash PROM Programming Options . . . . . . . . . . . . . . . . . . 115

Table 4-13: Xilinx Download Header Signal Description

for In-System SPI Flash PROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 4-14: PROM Generator Command Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 4-15: FPGA Timing Symbols for SPI Configuration Mode . . . . . . . . . . . . . . . . . . 134

Table 4-16: Configuration Timing Requirements for Attached SPI Serial Flash. . . . . . 135

Chapter 5: Master BPI Mode

Table 5-1: BPI Configuration Mode Differences between Spartan-3 Families . . . . . . . 140

Table 5-2: BPI Addressing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Table 5-3: Byte-Wide Peripheral Interface (BPI) Connections. . . . . . . . . . . . . . . . . . . . . . 142

Table 5-4: Example Compatible Parallel NOR Flash Families . . . . . . . . . . . . . . . . . . . . . 145

Table 5-5: Number of Bits to Program a Spartan-3E/3A FPGA

and Smallest Usable Parallel PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Table 5-6: Maximum ConfigRate Settings for Parallel Flash PROMs . . . . . . . . . . . . . . . 146

Table 5-7: FPGA Connections to Flash PROM with IO15/A-1 Pin . . . . . . . . . . . . . . . . . . 149

Table 5-8: Maximum ConfigRate Settings Using Parallel Platform Flash . . . . . . . . . . . 154

Table 5-9: Example Minimum Power-On to Setup Times

for Various Parallel NOR Flash PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 5-10: Configuration Timing Requirements for Attached Parallel NOR Flash . . 164

Table 5-11: Spartan-3E: Shared BPI Configuration Pins and Global Buffer Inputs . . . 165

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