USBN9603/4全速USB节点控制器手册：增强DMA支持

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USB N9603/9604 是 National Semiconductor 公司于 2003 年发布的一份官方技术手册，针对的是 Universal Serial Bus (USB) Full-Speed Node Controller。这份文档针对的是双功能控制器，它们在基本结构上几乎相同，除非特别指出，否则统称 "the device"。手册适用于 USB 1.0 和 1.1 规范版本，并且是 USB N9602 的增强版本。该设备的关键特性包括： 1. **集成性**：N9603/9604 集成了 USB 传输器、3.3V 电压调节器、串行接口引擎 (SIE)、USB 终端点 (EP) 队列、一个灵活的 8 位并行接口、时钟发生器以及 MICROWIRE/PLUS™ 接口，这些组件共同构成了一个完整的 USB 设备控制器。 2. **高级 DMA 支持**：N9603/9604 提供了增强的直接内存访问 (DMA) 功能，具备自动数据处理能力，能够优化数据传输效率，减轻主机处理器的负担。 3. **多端点管理**：设备支持七条独立的端点管道，其中一条用于强制性的控制端点，其余六条分别对应中断、批量和同步传输（异步）端点。每条端点管道都有自己的 FIFO（First In First Out 缓冲区），这使得数据交换更加高效。 4. **兼容性和升级性**：作为 USB 1.0 和 1.1 的高级版本，N9603/9604 能与当时的主流设备兼容，同时为未来的升级提供了基础。 5. **设计灵活性**：文档详细描述了设备的设计特点，有助于开发人员理解和实现 USB 设备的各种功能，如数据收发、配置、状态管理和错误处理等。 6. **时钟和复位机制**：虽然未在部分摘录中详述，但时钟生成电路的重置机制对于确保设备正常工作至关重要，它可能涉及到时钟同步和稳定性控制。通过阅读这份手册，开发者可以了解到如何利用 N9603/9604 控制器构建高性能、兼容性好的 USB 设备，包括硬件设计、驱动编程和系统集成的最佳实践。这对于电子工程师和系统设计师来说是一份极其宝贵的参考资料。

www.national.com

USBN9603/USBN9604

2.0 Functional Overview

The device is a Universal Serial Bus (USB) Node controller compatible with USB Specification, 1.0 and 1.1. It integrates onto

a single IC the required USB transceiver with a 3.3V regulator, the Serial Interface Engine (SIE), USB endpoint FIFOs, a

versatile (8-bit parallel or serial) interface and a clock generator. A total of seven endpoint pipes are supported: one bidirec-

tional for the mandatory control EP0 and an additional six for unidirectional endpoints to support USB interrupt, bulk and

isochronous data transfers. The 8-bit parallel interface supports multiplexed and non-multiplexed style CPU address/data

buses. The synchronous serial MICROWIRE interface allows adapting to CPUs without external address/data buses. A pro-

grammable interrupt output scheme allows adapting to different interrupt signaling requirements.

Refer to Figure 2 for the major functional blocks, described in the following sections.

2.1 TRANSCEIVER

The device contains a high-speed transceiver which consists of three main functional blocks:

— Differential receiver

— Single-ended receiver with on-chip voltage reference

— Transmitter with on-chip current source.

This transceiver meets the performance requirements described in Chapter 7 of the USB Specification, Version 1.1.

To minimize signal skew, the differential output swings of the transmitter are well balanced. Slew-rate control is used on the

driver to minimize radiated noise and crosstalk. The drivers support TRI-STATE operation to allow bidirectional, half-duplex

operation of the transceiver.

The differential receiver operates over the complete common mode range, and has a delay guaranteed to be larger than

that of the single-ended receivers. This avoids potential glitches in the Serial Interface Engine (SIE) after single-ended ze-

ros.

Single-ended receivers are present on each of the two data lines. These are required, in addition to the differential receiver, to

detect an absolute voltage with a switching threshold between 0.8V and 2.0V (TTL inputs). To increase V

rejection, without

glitching, a voltage reference sets the single-ended switching reference. An external 1.5 ± 5% KΩ resistor is required on D+ to

indicate that this is a high-speed node. This resistor should be tied to a voltage source between 3.0V and 3.6V, and referenced

to the local ground, such as the output provided on pin V3.3.

2.2 VOLTAGE REGULATOR (VREG)

The voltage regulator provides 3.3V for the integrated transceiver from 5.0V device power or USB bus power. This output

can be used to supply power to the 1.5 KΩ pull-up resistor. This output must be decoupled with a 1 µF tantalum capacitor

to ground. It can be disabled under software control to allow using the device in a 3.3V system.

2.3 SERIAL INTERFACE ENGINE (SIE)

The SIE is comprised of physical (PHY) and Media Access Controller (MAC) modules. The PHY module includes the digital-

clock recovery circuit, a digital glitch filter, End Of Packet (EOP) detection circuitry, and bit stuffing and unstuffing logic. The

MAC module includes packet formatting, CRC generation and checking, and endpoint address detection. It provides the

necessary control to give the NAK, ACK and STALL responses as determined by the Endpoint Pipe Controller (EPC) for the

specified endpoint pipe. The SIE is also responsible for detecting and reporting USB-specific events, such as NodeReset,

NodeSuspend and NodeResume. The module output signals to the transceiver are well matched (under 1 nS) to minimize

skew on the USB signals.

The USB specifications assign bit stuffing and unstuffing as the method to ensure adequate electrical transitions on the line

to enable clock recovery at the receiving end. The bit stuffing block ensures that whenever a string of consecutive 1’s is

encountered, a 0 is inserted after every sixth 1 in the data stream. The bit unstuffing logic reverses this process.

The clock recovery block uses the incoming NRZI data to extract a data clock (12 MHz) from a 48 MHz input clock. This

input clock is derived from a 24 MHz oscillator in conjunction with PLL circuitry (clock doubler). This clock is used in the data

recovery circuit. The output of this block is binary data (decoded from the NRZI stream) which can be appropriately sampled

using the extracted 12 MHz clock. The jitter performance and timing characteristics meet the requirements set forth in Chap-

ter 7 of the USB Specification.

Obsolete

2.0 Functional Overview (Continued)

www.national.com

USBN9603/USBN9604

2.4 ENDPOINT PIPE CONTROLLER (EPC)

The EPC provides the interface for USB function endpoints. An endpoint is the ultimate source or sink of data. An endpoint

pipe facilitates the movement of data between USB and memory, and completes the path between the USB host and the

function endpoint. According to the USB specification, up to 31 such endpoints are supported at any given time. USB allows

a total of 16 unidirectional endpoints for receive and 16 for transmit. As the control endpoint 0 is always bidirectional, the

total number is 31. Seven endpoint pipes with the same function address are supported. See Figure 3 for a schematic dia-

gram of EPC operation.

A USB function is a USB device that is able to transmit and receive information on the bus. A function may have one or more

configurations, each of which defines the interfaces that make up the device. Each interface, in turn, is composed of one or

more endpoints.

Each endpoint is an addressable entity on USB and is required to respond to IN and OUT tokens from the USB host (typically

a PC). IN tokens indicate that the host has requested to receive information from an endpoint, and OUT tokens indicate that

it is about to send information to an endpoint.

On detection of an IN token addressed to an endpoint, the endpoint pipe should respond with a data packet. If the endpoint

pipe is currently stalled, a STALL handshake packet is sent under software control. If the endpoint pipe is enabled but no

data is present, a NAK (Negative Acknowledgment) handshake packet is sent automatically. If the endpoint pipe is isochro-

nous and enabled but no data is present, a bit stuff error followed by an end of packet is sent on the bus.

Similarly, on detection of an OUT token addressed to an endpoint, the endpoint pipe should receive a data packet sent by

the host and load it into the appropriate FIFO. If the endpoint pipe is stalled, a STALL handshake packet is sent. If the end-

point pipe is enabled but no buffer is present for data storage, a NAK handshake packet is sent. If the endpoint is isochro-

nous and enabled but cannot handle the data, no handshake packet is sent.

A disabled endpoint does not respond to IN, OUT, or SETUP tokens.

The EPC maintains separate status and control information for each endpoint pipe.

For IN tokens, the EPC transfers data from the associated FIFO to the host. For OUT tokens, the EPC transfers data in the

opposite direction.

Figure 3. EPC Operation

2.5 MICROCONTROLLER INTERFACE

The device can be connected to a CPU or microcontroller via the 8-bit parallel or MICROWIRE interface. The interface type

is selected by the input mode pins MODE0 and MODE1. In addition, a configurable interrupt output is provided. The interrupt

type can be configured to be either open-drain active-low or push-pull active high or low.

Control Endpoint Pipe

FIFOs

Control Registers

EP0

Receive Endpoint Pipes

EPC.

FIFO

Control Registers

Transmit Endpoint Pipes

FIFO

Control Registers

USB SIE

USB

Function

Address

Compare

DMA

Microcontroller

Interface

EPB

EPA

Controller

EPX

EPY

EPZ

Obsolete

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