BCM5338M: 集成10/100BASE-T/TX 9端口交换芯片数据手册

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"5338M-DS02-RD.pdf" BCM5338M是一款集成化的10/100BASE-T/TX 9端口交换芯片，由博通（Broadcom）公司设计。这款芯片是基于其前代产品BCM5328和BCM5328M的第六代升级版，旨在提供高性能、高集成度的网络解决方案。它将高速交换系统所需的所有组件，如数据包缓冲区、物理层收发器（PHY）、媒体访问控制器（MAC）、地址管理和非阻塞交换架构集成到一个0.18微米的CMOS芯片中。该芯片遵循IEEE 802.3、802.3u和802.3x标准，确保与所有标准以太网和快速以太网设备的兼容性。这包括对MAC控制PAUSE帧的支持，以及自动协商功能，允许设备间灵活地协商最佳连接速度和双工模式。 BCM5338M包含了八个全双工10BASE-T/100BASE-TX快速以太网收发器。每个收发器都能处理10BASE-T以太网在Cat3、4或5类非屏蔽双绞线（UTP）上的物理层接口功能，以及在Cat5 UTP线缆上的100BASE-TX快速以太网。这意味着芯片能够支持多种线缆类型，以适应不同的安装环境和距离需求。在功能特性方面，BCM5338M提供了以下关键优势： 1. 非阻塞交换架构：确保数据流在所有端口间无冲突地传输，优化网络性能。 2. 内部数据包缓冲：允许在网络流量高峰时暂时存储数据，防止丢包。 3. 地址管理：有效处理多播、广播和未知单播帧，确保网络稳定运行。 4. PHY收发器：支持线缆诊断和故障检测功能，提高网络维护效率。 5. 自动协商：与连接设备自动协商最合适的速率和双工模式，简化配置过程。 6. PAUSE帧支持：通过流量控制机制，避免因接收端处理能力不足而导致的数据溢出。此外，BCM5338M可能还包含其他高级特性，如端口镜像、QoS（服务质量）策略、VLAN（虚拟局域网）支持以及端口安全功能，以增强网络管理和安全性。这些特性对于企业级网络环境尤其重要，可以实现网络的精细化管理和高效运行。总而言之，BCM5338M是一款高度集成的交换芯片，适用于需要高带宽、低延迟和灵活配置的网络应用，如路由器、企业级交换机和家庭网络中心等。通过其丰富的功能和对标准的全面支持，它为构建可靠的以太网网络提供了坚实的基础。

■ BCM5338M Advance Data Sheet

07/16/03

Broadcom Corporation

Page xvi Document 5338M-DS02-R

LIST OF FIGURES

Figure 1: Functional Block Diagram................................................................................................................. i

Figure 2: Normal SPI Command Byte ............................................................................................................9

Figure 3: Fast SPI Command Byte ...............................................................................................................10

Figure 4: SPI Serial Management Port Interface Write Operation................................................................10

Figure 5: SPI Serial Management Port Interface Read Operation................................................................10

Figure 6: Normal SPI Mode Read Flow Chart ..............................................................................................12

Figure 7: Normal SPI Mode Write Flow Chart ..............................................................................................13

Figure 8: BCM5338M Mode Address Table Organization ............................................................................16

Figure 9: Transmit Output Queues ...............................................................................................................29

Figure 10: Transmit MIB Autocast Frame Format ..........................................................................................38

Figure 11: MAC-to-MAC MII Connection ........................................................................................................40

Figure 12: Turbo MII Block Diagram...............................................................................................................41

Figure 13: MII-Compliant MAC with BCM5338M............................................................................................42

Figure 14: Transmit/Receive Frame Format Over Management Port ............................................................43

Figure 15: BRCM Tag Format ........................................................................................................................44

Figure 16: Expansion Port Interface with Two BCM5338Ms ..........................................................................47

Figure 17: Expansion Port Interface with Daisy-Chained BCM5338Ms .........................................................48

Figure 18: Simple Port Mirroring Example......................................................................................................52

Figure 19: Static MAC Security Table.............................................................................................................57

Figure 20: Format and Addressing of the Static MAC Table ..........................................................................58

Figure 21: Serial LED Shift Sequence ............................................................................................................63

Figure 22: Partial Example External Circuit for Serial LED Mode...................................................................65

Figure 23: Serial EEPROM Connection..........................................................................................................67

Figure 24: Reset and Clock Timing ..............................................................................................................199

Figure 25: Serial LED Timing........................................................................................................................200

Figure 26: MII Input Timings .........................................................................................................................201

Figure 27: RvMII Input Timings.....................................................................................................................202

Figure 28: MII Output Timings ......................................................................................................................203

Figure 29: RvMII Output Timings..................................................................................................................204

Figure 30: SPI Timings, SS

Asserted During SCK High...............................................................................205

Figure 31: SPI Timings, SS

Asserted During SCK Low................................................................................205

Figure 32: EEPROM Timing .........................................................................................................................206

■ BCM5338M Advance Data Sheet

07/16/03

Broadcom Corporation

Page xviii Document 5338M-DS02-R

LIST OF TABLES

Table 1: Flow Control Modes.........................................................................................................................8

Table 2: EEPROM Header Format..............................................................................................................15

Table 3: EEPROM Contents........................................................................................................................15

Table 4: Address Table Entry ......................................................................................................................17

Table 5: Behavior for Reserved Multicast Addresses..................................................................................18

Table 6: Multiple Spanning Tree State ........................................................................................................25

Table 7: Directly Supported MIB Counters ..................................................................................................34

Table 8: Indirectly Supported MIB Counters................................................................................................36

Table 9: BCM5338M Supported MIB Extensions ........................................................................................37

Table 10: OPCODE Field in BRCM Tag for Management Port Frame .........................................................44

Table 11: Fields in BRCM Tag for Management Port Frame ........................................................................45

Table 12: LED Status Types..........................................................................................................................63

Table 13: LED Mode Matrix...........................................................................................................................64

Table 14: Load Meter LED Decode ...............................................................................................................66

Table 15: MII Management Frame Format....................................................................................................68

Table 16: Signal Descriptions........................................................................................................................70

Table 17: Pin Assignment by Pin Number.....................................................................................................77

Table 18: Pin Assignment by Signal Name ...................................................................................................79

Table 19: Global Page Register Map ............................................................................................................81

Table 20: Control Registers (Page 00h) ........................................................................................................83

Table 21: 10/100 Port Control Register (Page 00h: Address 00d–07d, 00h–07h) ........................................84

Table 22: MII/IMP Port Control Register (Page 00h: Address 08d, 08h).......................................................85

Table 23: SMP Control Register (Page 00h: Address 10d, 0Ah) ..................................................................86

Table 24: Switch Mode Register (Page 00h: Address 11d, 0Bh) ..................................................................87

Table 25: MII Port State Override Register (Page 00h: Address 14d, 0Eh) ..................................................88

Table 26: Power Down Mode Register (Page 00h: Address 15d, 0Fh).........................................................88

Table 27: New Control Register (Page 00h: Address 33d, 21h) ..................................................................89

Table 28: WAN Port Select Register (Page 00h: Address 34-35d, 22-23h)..................................................89

Table 29: Protected Port Select Register (Page 00h: Address 36-37d, 24-25h)...........................................90

Table 30: Software Flow Control Register (Page 00h: Address 38-39d, 26-27h) .........................................90

Table 31: Unicast Lookup Fail Forward Map Register (Page 00h: Address 40-41d, 28-29h) .......................90

Table 32: Multicast Lookup Fail Forward Map Register (Page 00h: Address 42-43d, 2a-2bh).....................90

Advance Data Sheet ■ BCM5338M

07/16/03

Broadcom Corporation

Document 5338M-DS02-R Page xix

Table 33: Status Registers (Page 01h)......................................................................................................... 91

Table 34: Link Status Summary Register (Page 01h: Address 00dQQ–01d, 00h–01h) ............................... 92

Table 35: Link Status Change Register (Page 01h: Address 02d–03d, 02h–03h) ....................................... 93

Table 36: Port Speed Summary Register (Page 01h: Address 04d–05d, 04h–05h) .................................... 93

Table 37: Duplex Status Summary Register (Page 01h: Address 06d–07d, 06h–07h) ................................ 94

Table 38: Pause Status Summary Register (Page 01h: Address 08d–09d, 08h–09h)................................. 94

Table 39: Source Address Change Register (Page 01h: Address 12d–13d, 0Ch–0Dh) .............................. 94

Table 40: Last Source Address Port Registers (Page 01h) ..........................................................................95

Table 41: Last Source Address Port n (Page 01h: Address 16d–69d, 10h–45h) ......................................... 95

Table 42: BIST Status Register (Page 01h: Address 70d, 46h).................................................................... 96

Table 43: Management Mode Registers (Page 02h) .................................................................................... 97

Table 44: Global Management Configuration Register (Page 02h: Address 00d, 00h)................................ 98

Table 45: Management Port ID Register (Page 02h: Address 02d, 02h)...................................................... 99

Table 46: RMON MIB Steering Register (Page 02h: Address 04d–05d, 04h–05h)...................................... 99

Table 47: Aging Time Control Register (Page 02h: Address 06d–09d, 06h–09h)........................................ 99

Table 48: Mirror Capture Control Register (Page 02h: Address 16d–17d, 10h–11h)................................. 100

Table 49: Ingress Mirror Control Register (Page 02h: Address 16d–19d, 12h–13h) .................................. 101

Table 50: Ingress Mirror Divider Register (Page 02h: Address 20d–21d, 14h–15h) .................................. 101

Table 51: Ingress Mirror MAC Address Register (Page 02h: Address 22d–27d, 16h–1Bh)....................... 102

Table 52: Egress Mirror Control Register (Page 02h: Address 28d–29d, 1Ch–1Dh) ................................. 103

Table 53: Egress Mirror Divider Register (Page 02h: Address 30d–31d, 1Eh–1Fh) .................................. 104

Table 54: Egress Mirror MAC Address Register (Page 02h: Address 32d–37d, 20h–25h)........................ 104

Table 55: IGMP Control Register (Page 02h: Address 38d, 26h)............................................................... 104

Table 56: IGMP Replace DA Register (Page 02h: Address 39d–44d, 27h–2Ch)....................................... 105

Table 57: Chip Revision ID Register (Page 02h: Address 48d, 30h).......................................................... 105

Table 58: MIB Autocast Register (Page 03h).............................................................................................. 106

Table 59: MIB Autocast Port Register (Page 03h: Address 00dQ–01d, 00h–01h)..................................... 106

Table 60: MIB Autocast Header Pointer Register (Page 03h: Address 02d–03d, 02h–03h) ...................... 107

Table 61: MIB Autocast Header Length Register (Page 03h: Address 04d–05d, 04h–05h)....................... 107

Table 62: MIB Autocast Header Pointer Register (Page 03h: Address 06d–11d, 06h–0Bh)...................... 107

Table 63: MIB Autocast Header Pointer Register (Page 03h: Address 12d–17d, 0Ch–11h)...................... 108

Table 64: MIB Autocast Type Register (Page 03h: Address 18d–19d, 12h–13h) ...................................... 108

Table 65: MIB Autocast Rate Register (Page 03h: Address 20dQ–21d, 14h–15h).................................... 108

Table 66: ARL Control Registers (Page 04h).............................................................................................. 109

Table 67: Global ARL Configuration Register (Page 04h: Address 00d, 00h) ............................................ 109

■ BCM5338M Advance Data Sheet

07/16/03

Broadcom Corporation

Page xx Document 5338M-DS02-R

Table 68: BPDU Multicast Address Register (Page 04h: Address 04d-09d, 04h-09h) ...............................110

Table 69: Multiport Address 1 Register (Page 04h: Address 16d–21d, 10h–15h) ......................................110

Table 70: Multiport Vector 1 Register (Page 04h: Address 22d–23d, 16h–17h) .........................................111

Table 71: Multiport Address 2 Register (Page 04h: Address 32d–37d, 20h–25h) ......................................111

Table 72: Multiport Vector 2 Register (Page 04h: Address 38d–39d, 26h–27h) .........................................112

Table 73: Secure Source Port Mask Register (Page 04h: Addresses 48d-49d, 30h-31h) ..........................112

Table 74: Secure Destination Port Mask Register (Page 04h: Addresses 50d-51d, 32h-33h) ...................113

Table 75: ARL Access Registers (Page 05h) ..............................................................................................114

Table 76: ARL Read/Write Control Register (Page 05h: Address 0d, 0h)...................................................114

Table 77: MAC Address Index Register (Page 05h: Address 02d–07d, 02h–07h) .....................................115

Table 78: VID Table Index Register (Page 05h: Address 08d-09d, 08h-09h) .............................................115

Table 79: ARL Entry 0 Register (Page 05h: Address 16d–23d, 10h–17h)..................................................116

Table 80: ARL Entry 0 Register (Page 05h: Address 16d–23d, 10h–17h)..................................................117

Table 81: ARL Entry 1 Register (Page 05h: Address 24d–31d, 18h–1Fh)..................................................118

Table 82: ARL Entry 1 Register (Page 05h: Address 24d–31d, 18h–1Fh)..................................................119

Table 83: ARL Search Control Register (Page 05h: Address 32d, 20h) .....................................................120

Table 84: ARL Search Address Register (Page 05h: Address 34d–35d, 22h–23h)....................................120

Table 85: ARL Search Result Register (Page 05h: Address 16d–23d, 24h–2Bh) ......................................121

Table 86: ARL Search Result VID Register (Page 05h: Address 42d–43d, 2Ch–2Dh) ..............................122

Table 87: VID Entry 0 Register (Page 05h: Address 48d-49d, 30h-31h) ....................................................122

Table 88: VID Entry 1 Register (Page 05h: Address 50d-51d, 32h-33h) ....................................................122

Table 89: Management Frame Access Registers (Page 06h).....................................................................123

Table 90: Management Frame Read Data Register (Page 06h: Address 00d, 00h)...................................123

Table 91: Management Frame Write Data Register (Page 06h: Address 01d, 01h)...................................123

Table 92: Management Frame Write Control Register (Page 06h: Address 02-03d, 02-03h) ....................124

Table 93: Management Frame Read Status Register (Page 06h: Address 04d–05d, 04h–05h) ................125

Table 94: Generic Memory Access Registers (Page 08h) ..........................................................................126

Table 95: Memory Read/Write Control Register (Page 08h: Address 00-03d, 00-03h) ..............................126

Table 96: Memory Read/Write Data Register (Page 08h: Address 04d-011d, 04-0Bh)..............................127

Table 97: Memory Read/Write VID_Data Register (Page 08h: Address 16d, 10h).....................................127

Table 98: Priority Queue Control Registers (Page 0Ah)..............................................................................128

Table 99: Global Flow Control Register (Page 0Ah: Address 30-31h) ........................................................128

Table 100: Queue 0 TxDsc Control 3 Register (Page 0Ah: Address 64-65h) ...............................................129

Table 101: Queue 1 TxDsc Control 3 Register (Page 0Ah: Address 72-73h) ...............................................129

Table 102: Queue 2 TxDsc Control 3 Register (Page 0Ah: Address 80-81h) ...............................................130

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