高性能数据中心以太网重定时器DS100DF410的技术规格和应用范例

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The TI-DS100RT410.pdf document provides information on the Ethernet re-timer module DS100RT410, which is used in various networking equipment such as line cards, switch fabrics, ASICs, backplanes, and optical modules. The DS100RT410 is designed to improve signal integrity and reduce noise in high-speed Ethernet connections, especially in 10GbE (10 Gigabit Ethernet) applications. The DS100RT410 module features advanced technologies such as passive copper and ASIC components to enhance signal quality and performance. It is capable of handling noisy signals and transforming them into clean, reliable signals for uninterrupted data transmission. The module is designed to be compatible with various connector types, including SFP (Small Form-factor Pluggable) and QSFP (Quad Small Form-factor Pluggable) connectors, making it versatile and suitable for a wide range of networking devices. Overall, the DS100RT410 Ethernet re-timer module is a critical component in ensuring efficient and reliable data transmission in high-speed Ethernet networks. Its advanced features and compatibility with different connector types make it a valuable solution for improving signal integrity and reducing noise in networking equipment. For more detailed information, please refer to the product folder and sample provided in the document.

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-0.5

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VOD (V)

TIME (UI)

DS100RT410

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Feature Description (continued)

7.3.3 CTLE

The CTLE in the DS125DF410 is a fully adaptive equalizer with optional limiting stage. The CTLE adapts

according to a figure of merit (FOM) calculation during the lock acquisition process. Once the CDR has locked

and the CTLE has been adapted, the CTLE boost level will be frozen until a manual re-adapt command is issued

or until the CDR re-enters the lock acquisition state. The CTLE is typically readapted by resetting the CDR. The

CTLE consists of 4 stages, with each stage having 2-bit boost control. This allows for 256 different stage-boost

combinations. The CTLE adaption algorithm allows the CTLE to adapt through 32 of these stage-boost

combinations. These 32 stage-boost combinations comprise the EQ Table in the channel registers; see channel

registers 0x40 through 0x5F. This EQ Table can be reprogrammed to support up to 32 of the 256 stage-boost

settings.

CTLE boost levels are determined by summing the boosts levels of the four stages. Different stage-boost

combinations that sum to the same number will have approximately the same boost level, but will result in a

different shape for the EQ transfer function (boost curve).

The fourth stage in the CTLE can be programmed through the SMBus interface to become a limiting stage rather

than a linear stage.

7.3.4 Clock and Data Recovery

The DS100RT410 performs its clock and data recovery function by detecting the bit transitions in the incoming

data stream and locking its internal VCO to the clock represented by the mean arrival times of these bit

transitions. This process produces a recovered clock with jitter which is greatly reduced for jitter frequencies

outside the bandwidth of the CDR phase-locked loop (PLL). This is the primary benefit of using the DS100RT410

in a system. It significantly reduces the jitter present in the data stream, in effect resetting the jitter budget for the

system.

7.3.5 Output Driver

The output driver is capable of driving variable output voltages with variable amounts of analog de-emphasis.

The output voltage and de-emphasis level can be configured by writing registers over the SMBus. The

DS100RT410 cannot determine independently the appropriate output voltage or de-emphasis setting, so the user

is responsible for configuring these parameters. They can be set for each channel independently.

An idealized transmit waveform with analog de-emphasis applied is listed in Figure 4.

Figure 4. Idealized De-Emphasis Waveform

7.3.6 CTLE Boost Setting

The CTLE is a four-stage amplifier with an adjustable, quasi-high-pass transfer function on each stage. The

overall frequency response of the CTLE is set by adjusting the boost of each stage independently. Each stage of

the CTLE can be set to one of four boost settings. The amount of high-frequency boost supplied by each stage

generally increases with increasing boost settings.

The CTLE can also be configured to adapt automatically to provide the optimum boost level for its input signal.

Automatic adaptation of the CTLE only is the default mode of operation for the DS100RT410.

DS100RT410

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Feature Description (continued)

7.3.7 Driver Output Voltage

The differential output voltage of the DS100RT410 can be configured from a nominal setting of 600-mV peak-to-

peak differential to a nominal setting of 1.3-V peak-to-peak differential, depending upon the application. The

driver output voltage as set is the typical peak-to-peak differential output voltage with no de-emphasis enabled.

7.3.8 Driver Output De-Emphasis

The output de-emphasis level of the DS100RT410 can be configured from a nominal setting of 0 dB to a nominal

setting of –12 dB depending upon the application. Larger absolute values of the de-emphasis setting provide

more pre-distortion of the output driver waveform, accentuating the high-frequency components of the output

driver waveform relative to the low-frequency components. Greater values of de-emphasis can compensate for

greater dispersion in the transmission media at the output of the DS100RT410. The output de-emphasis level as

set is the typical value to which the output signal will settle following the de-emphasis pulse interval in dB relative

to the output VOD.

7.3.9 Driver Output Rise and Fall Time

In some applications, a longer rise and fall time for the output signal is desired. This can reduce electromagnetic

interference (EMI) generated by fast switching waveforms. This is necessary in some applications for regulatory

compliance. In others, it can reduce the crosstalk in the system.

The DS100RT410 can be configured to operate with a nominal rise/fall time corresponding to the maximum slew

rate of the output drivers into the load capacitance. Alternatively, the DS100RT410 can be configured to operate

with a slightly greater rise and fall time if desired. For the typical specifications on rise and fall time, see Electrical

Characteristics.

7.3.10 Ref_mode 0 Mode (Reference Clock Not Required)

The DS100RT410 can be used without using a reference clock and the input REFCLK_IN pin can be open.

When register 0x36, bits [5:4] are set to 2’b00, the device operates without using a reference clock at

10.3125-Gbps mode.

For 1-GbE applications, it is required to bypass the CDR by setting the override bit 5 of register 0x09 to 1, and

set the data mux bits [7:5] to 3'b000 of register 0x1E.

7.3.11 Ref_mode 3 Mode (Reference Clock Required)

When using ref_mode 3, the device uses an external 25-MHz clock. This mode of operation is set in register

0x36 bits [5:4] = 2'b11 and is the default setting. In ref_mode 3, the external reference clock is used to aid initial

phase lock, and to determine when its VCO is properly phase-locked. An external oscillator should be used to

generate a 2.5-V, 25-MHz reference signal which is connected to the DS100RT410 on the reference clock input

pin (pin 19). The DS100RT410 does not include a crystal oscillator circuit, so a stand-alone external oscillator is

required.

The reference clock speeds up the initial phase lock acquisition. The DS100RT410 is set to phase lock to a

known data rate, or a constrained set of known data rates, and the digital circuitry in the DS100RT410 pre-

configures the VCO frequency. This enables the DS100RT410 phase-lock to the incoming signal very quickly.

The reference clock is used to calibrate the VCO coarse tuning. However, the reference clock is not synchronous

to the data stream, and the quality of the reference clock does not affect the jitter on the output retimed data. The

retimed data clock for each channel is synchronous to the VCO internal to that channel of the DS100RT410.

The phase noise of the reference clock is not critical. Any commercially-available 25-MHz oscillator can provide

an acceptable reference clock. The reference clock can be daisy-chained from one retimer to another so that

only one reference oscillator is required in a system.

7.3.12 False Lock Detector Setting

The register 0x2F, bit 1 is set to 1 by default, which disables the false lock detector. This bit must be set to 0 to

enable the false lock detector function.

DS100RT410

ZHCSEC0A –JANUARY 2013–REVISED OCTOBER 2015

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Feature Description (continued)

7.3.13 Reference Clock In

REFCLK_IN pin 19 is for reference clock input. A 25-MHz oscillator should be connected to pin 19. See Electrical

Characteristics for the requirements on the 25-MHz clock. The frequency of the reference clock should always be

25 MHz no matter what data rate or mode of operation is used.

7.3.14 Reference Clock Out

REFCLK_OUT pin 42 is the reference clock output pin. The DS100RT410 drives a buffered replica of the

25-MHz reference clock input on this output pin. If there are multiple DS100RT410 in the system, the

REFCLK_OUT pin can be directly connected to the REFCLK_IN pin of another DS100RT410 in a daisy chain

connection. The other option is to connect the external 25-MHz oscillator to a clock fanout buffer to distribute the

25-MHz clock to each DS100RT410, which ensures there is a reference clock for the DS100RT410.

7.3.15 Daisy Chain of REFCLK_OUT to REFCLK_IN

When daisy chaining the device REFCLK_OUT to the REFCLK_IN of another device, the trace connection

should be less than 1.5 inches (about 5-pF trace capacitance) and it is possible to cascade up to 9 devices.

While in other systems with longer interconnecting trace or more capacitive loading, the daisy chain of multiple

devices should be reduced. In a system which requires longer daisy chain, it is recommended to place an

inverted gate after the sixth device. The pre-distorted duty cycle from the inverter allows longer daisy chain. A

better approach is to break the long daisy chain into shorter chains, each driven by a buffer version of the clock

distribution and with each chain kept to a maximum of 6 cascade devices. As an example, if there are 12 devices

in the system, the daisy chain connections can be divided into two groups of 6 devices and PCB trace length for

the reference clock output to input connection; each should be 1.5 inch or less.

7.3.16 INT

The INT line is an open-drain, 3.3-V tolerant, LVCMOS active-low output. The INT lines from multiple

DS100RT410 devices can be wired together and connected to an external controller.

The DS100RT410 generates an interrupt when it detects a loss of signal after previously detecting the presence

of a signal, or when it detects loss of lock after previously detecting phase lock. These interrupts are always

enabled. In addition, the horizontal eye opening/vertical eye opening (HEO/VEO) interrupt can be enabled using

SMBus control for each channel independently. This interrupt is disabled by default. The thresholds for horizontal

and vertical eye opening that will trigger the interrupt can be set using the SMBus control for each channel.

If any interrupt occurs, registers in the DS100RT410 latch in information about the event that caused the

interrupt. This can then be read out by the controller over the SMBus.

7.3.17 LOCK_3, LOCK_2, LOCK_1, and LOCK_0

Each channel of the DS100RT410 has an independent lock indication pin. These lock indication pins, LOCK_3,

LOCK_2, LOCK_1, and LOCK_0, are pin 16, pin 21, pin 40, and pin 45 respectively. These pins are shared with

the SMBus address strap lines. After the address values have been latched in on power-up, these lines revert to

their lock indication function.

When the corresponding channel of the DS100RT410 is locked to the incoming data stream, the lock indication

pin goes high. This pin can be used to drive an LED on the board, giving a visual indication of the lock status, or

it can be connected to other circuitry which can interpret the lock status of the channel.

7.4 Device Functional Modes

The DS100RT410 can be configured using two different methods.

• SMBus Master Configuration Mode

• SMBus Slave Configuration Mode

The configuration mode is selected by the state of the EN_SMB pin (pin 20) when the DS100RT410 is powered-

up. This pin should be either left floating or tied to the device V

through an optional 1-kΩ resistor. The effect of

each of these settings is listed in Table 1.

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