直流电机控制器直流电机控制器VHDL源程序源程序
本文为大家提供一个直流电机控制器VHDL的源程序。
LIBRARY IEEE;
USE IEEE.Std_logic_1164.ALL;
USE IEEE.Std_logic_unsigned.All;
USE IEEE.Std_logic_arith.All;
ENTITY Dccount IS
Port (
Clk : IN STD_LOGIC;
AI : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CO : Out STD_LOGIC_VECTOR(3 DOWNTO 0);
Pulse: IN STD_LOGIC;
DriverA,DriverB: OUT STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
Sp : Out STD_LOGIC);
END Dccount;
ARCHITECTURE A OF Dccount IS
SIGNAL F: STD_LOGIC_VECTOR(5 Downto 0);
SIGNAL F_hz: STD_LOGIC;
SIGNAL OSC: STD_LOGIC;
SIGNAL OSC1: STD_LOGIC;
SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL A: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CODE: STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL Bcd:STD_LOGIC_VECTOR(23 Downto 0);
SIGNAL COUNT:STD_LOGIC_VECTOR(23 Downto 0);
SIGNAL SUM: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL D: STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
SIGNAL Ind_coil: STD_LOGIC_VECTOR(3 Downto 0) := "0001";
SIGNAL Hz:STD_LOGIC;
SIGNAL Spo: STD_LOGIC;
SIGNAL SW:STD_LOGIC;
SIGNAL KEY:STD_LOGIC;
SIGNAL DRA,DRB:STD_LOGIC;
BEGIN
DRIVERA<=DRA;
DRIVERB<=DRB;
P(5 Downto 0) <= F(5 Downto 0);
CO(3 DOWNTO 0) <=C(3 DOWNTO 0);