VHDL设计：0-24小时电子钟+闹钟与整点报时功能

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock is
port(clk:in std_logic;
        clk1:in std_logic;
        md1:in std_logic;
        md2:in std_logic_vector(1 downto 0);
        speak:out std_logic;
        douth1:out std_logic_vector(3 downto 0);
        douth2:out std_logic_vector(3 downto 0);
        doutm1:out std_logic_vector(3 downto 0);
        doutm2:out std_logic_vector(3 downto 0);
        douts1:out std_logic_vector(3 downto 0);
        douts2:out std_logic_vector(3 downto 0));
end clock;
architecture one of clock is
signal hou1:std_logic_vector(3 downto 0);
signal hou2:std_logic_vector(3 downto 0);
signal min1:std_logic_vector(3 downto 0);
signal min2:std_logic_vector(3 downto 0);
signal seth1:std_logic_vector(3 downto 0);
signal seth2:std_logic_vector(3 downto 0);
signal setm1:std_logic_vector(3 downto 0);
signal setm2:std_logic_vector(3 downto 0);
signal sec1:std_logic_vector(3 downto 0);
signal sec2:std_logic_vector(3 downto 0);
signal h1:std_logic_vector(3 downto 0);
signal h2:std_logic_vector(3 downto 0);
signal m1:std_logic_vector(3 downto 0);

signal m2:std_logic_vector(3 downto 0);
signal s1:std_logic_vector(3 downto 0);
signal s2:std_logic_vector(3 downto 0);
begin
h110:process(clk,hou2,min1,min2,sec1,sec2,md1,md2)
begin
if clk'event and clk='1' then
if (hou1="0010" and hou2="0011")and(((min1="0101" and min2="1001") and (sec1="0101" and sec2="1001"))or (md1='0' and md2="10")) then
hou1<="0000";
elsif (hou2="1001"and(min1="0101" and min2="1001") and (sec1="0101" and sec2="1001")) then
hou1<=hou1+1;
elsif md1='0' and md2="10" and hou2="1001" then hou1<=hou1+1;
end if;
end if;
end process h110;
h220:process(clk,min1,min2,sec1,sec2,md1,md2,hou1)
begin
if clk'event and clk='1' then
if (hou1="0010" and hou2="0011")and(((min1="0101" and min2="1001") and (sec1="0101" and sec2="1001"))or (md1='0' and md2="10")) then
hou2<="0000";
elsif hou2="1001"and(min1="0101" and min2="1001") and (sec1="0101" and sec2="1001") then
hou2<="0000";
elsif md1='0' and md2="10" and hou2="1001" then hou2<="0000";
elsif ((min1="0101" and min2="1001") and (sec1="0101" and sec2="1001")) or (md1='0' and md2="10") then
hou2<=hou2+1;
end if;
end if;
end process h220;
m110:process(clk,min2,sec1,sec2)
begin