TMS320C6713BGDP数据手册

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TMS320C6713, TMS320C6713B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

D Highest-Performance Floating-Point Digital

Signal Processors (DSPs): C6713/C6713B

− Eight 32-Bit Instructions/Cycle

− 32/64-Bit Data Word

− 300-, 225-, 200-MHz (GDP), and 200-,

167-MHz (PYP) Clock Rates

− 3.3-, 4.4-, 5-, 6-Instruction Cycle Times

− 2400/1800, 1800 /1350 , 1600 /1200 , and

1336 /1000 MIPS /MFLOPS

− Rich Peripheral Set, Optimized for Audio

− Highly Optimized C/C++ Compiler

D Advanced Very Long Instruction Word

(VLIW) TMS320C67x DSP Core

− Eight Independent Functional Units:

− Two ALUs (Fixed-Point)

− Four ALUs (Floating- and Fixed-Point)

− Two Multipliers (Floating- and

Fixed-Point)

− Load-Store Architecture With 32 32-Bit

General-Purpose Registers

− Instruction Packing Reduces Code Size

− All Instructions Conditional

D Instruction Set Features

− Native Instructions for IEEE 754

− Single- and Double-Precision

− Byte-Addressable (8-, 16-, 32-Bit Data)

− 8-Bit Overflow Protection

− Saturation; Bit-Field Extract, Set, Clear;

Bit-Counting; Normalization

D L1/L2 Memory Architecture

− 4K-Byte L1P Program Cache

(Direct-Mapped)

− 4K-Byte L1D Data Cache (2-Way)

− 256K-Byte L2 Memory Total: 64K-Byte

L2 Unified Cache/Mapped RAM, and

192K-Byte Additional L2 Mapped RAM

D Device Configuration

− Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot

− Endianness: Little Endian, Big Endian

D 32-Bit External Memory Interface (EMIF)

− Glueless Interface to SRAM, EPROM,

Flash, SBSRAM, and SDRAM

− 512M-Byte Total Addressable External

Memory Space

D Enhanced Direct-Memory-Access (EDMA)

Controller (16 Independent Channels)

D 16-Bit Host-Port Interface (HPI)

D Two Multichannel Audio Serial Ports

(McASPs)

− Two Independent Clock Zones Each

(1 TX and 1 RX)

− Eight Serial Data Pins Per Port:

Individually Assignable to any of the

Clock Zones

− Each Clock Zone Includes:

− Programmable Clock Generator

− Programmable Frame Sync Generator

− TDM Streams From 2-32 Time Slots

− Support for Slot Size:

8, 12, 16, 20, 24, 28, 32 Bits

− Data Formatter for Bit Manipulation

− Wide Variety of I2S and Similar Bit

Stream Formats

− Integrated Digital Audio Interface

Transmitter (DIT) Supports:

− S/PDIF, IEC60958-1, AES-3, CP-430

Formats

− Up to 16 transmit pins

− Enhanced Channel Status/User Data

− Extensive Error Checking and Recovery

D Two Inter-Integrated Circuit Bus (I

C Bus)

Multi-Master and Slave Interfaces

D Two Multichannel Buffered Serial Ports:

− Serial-Peripheral-Interface (SPI)

− High-Speed TDM Interface

− AC97 Interface

D Two 32-Bit General-Purpose Timers

D Dedicated GPIO Module With 16 pins

(External Interrupt Capable)

D Flexible Phase-Locked-Loop (PLL) Based

Clock Generator Module

D IEEE-1149.1 (JTAG

†

)

Boundary-Scan-Compatible

D Package Options:

− 208-Pin PowerPAD Plastic (Low-Profile)

Quad Flatpack (PYP)

− 272-Ball, Ball Grid Array Package (GDP)

D 0.13-µm/6-Level Copper Metal Process

− CMOS Technology

D 3.3-V I/Os, 1.2

‡

-V Internal (GDP & PYP)

D 3.3-V I/Os, 1.4-V Internal (GDP) (300 MHz

only)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

This document contains information on products in more than one phase

of development. The status of each device is indicated on the page(s)

specifying its electrical characteristics.

TMS320C67x and PowerPAD are trademarks of Texas Instruments.

C Bus is a trademark of Philips Electronics N.V. Corporation

All trademarks are the property of their respective owners.

†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

‡

These values are compatible with existing 1.26V designs.

TMS320C6713, TMS320C6713B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Table of Contents

EMIF device speed 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EMIF big endian mode correctness [C6713B only] 95. . .

bootmode 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

absolute maximum ratings over operating case

temperature range 97. . . . . . . . . . . . . . . . . . . . . . . . . .

recommended operating conditions 98. . . . . . . . . . . . . . . .

electrical characteristics over recommended ranges of

supply voltage and operating case temperature 99.

parameter measurement information 100. . . . . . . . . . . . . .

signal transition levels 100. . . . . . . . . . . . . . . . . . . . . . . . . . .

timing parameters and board routing analysis 101. . . . . .

input and output clocks 103. . . . . . . . . . . . . . . . . . . . . . . . . .

asynchronous memory timing 107. . . . . . . . . . . . . . . . . . . .

synchronous-burst memory timing 110. . . . . . . . . . . . . . . .

synchronous DRAM timing 112. . . . . . . . . . . . . . . . . . . . . . .

HOLD

/HOLDA timing 118. . . . . . . . . . . . . . . . . . . . . . . . . . .

BUSREQ timing 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

reset timing 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

external interrupt timing 122. . . . . . . . . . . . . . . . . . . . . . . . .

multichannel audio serial port (McASP) timing 123. . . . . .

inter-integrated circuits (I2C) timing 126. . . . . . . . . . . . . . .

host-port interface timing 129. . . . . . . . . . . . . . . . . . . . . . . .

multichannel buffered serial port timing 133. . . . . . . . . . . .

timer timing 143. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

general-purpose input/output (GPIO) port timing 144. . . .

JTAG test-port timing 145. . . . . . . . . . . . . . . . . . . . . . . . . . .

mechanical data 146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

revision history 149. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GDP 272-Ball BGA package (bottom view) 3. . . . . . . . . . . . .

PYP PowerPAD QFP package (top view) 8. . . . . . . . . . . . .

description 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

device characteristics 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

functional block and CPU (DSP core) diagram 12. . . . . . . . . .

CPU (DSP core) description 13. . . . . . . . . . . . . . . . . . . . . . . . .

memory map summary 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

peripheral register descriptions 17. . . . . . . . . . . . . . . . . . . . . . .

signal groups description 26. . . . . . . . . . . . . . . . . . . . . . . . . . . .

device configurations 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

configuration examples 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

debugging considerations 45. . . . . . . . . . . . . . . . . . . . . . . . . . .

terminal functions 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

development support 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

documentation support 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CPU CSR register description 66. . . . . . . . . . . . . . . . . . . . . . . .

cache configuration (CCFG) register description (13B) 68. . .

interrupts and interrupt selector 69. . . . . . . . . . . . . . . . . . . . . . .

external interrupt sources 71. . . . . . . . . . . . . . . . . . . . . . . . . . . .

EDMA module and EDMA selector 72. . . . . . . . . . . . . . . . . . . .

PLL and PLL controller 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

multichannel audio serial port (McASP) peripherals 82. . . . .

I2C 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

general-purpose input/output (GPIO) 88. . . . . . . . . . . . . . . . . .

power-down mode logic 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

power-supply sequencing 91. . . . . . . . . . . . . . . . . . . . . . . . . . . .

power-supply decoupling 92. . . . . . . . . . . . . . . . . . . . . . . . . . . .

IEEE 1149.1 JTAG compatibility statement 92. . . . . . . . . . . . .

剩余149页未读，继续阅读

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2013-11-15

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