ARM Cortex-M3权威指南：深入解析

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"The definitive guide to the ARM Cortex-M3" 这篇资源是"The definitive guide to the ARM Cortex-M3"的英文原版第二版，是一本详细深入介绍ARM Cortex-M3微处理器的专业指南。ARM Cortex-M3是ARM公司设计的一种高效能、低功耗的32位微控制器系列，广泛应用于嵌入式系统、物联网设备以及各种工业控制应用。本书涵盖了Cortex-M3架构的核心特性，包括其RISC（精简指令集计算机）设计、Thumb-2指令集、中断处理机制、硬件浮点单元（如果支持的话）、存储器系统以及调试接口。作者详细阐述了Cortex-M3的体系结构，帮助读者理解如何有效地利用其性能。在书中，读者可以找到关于编程模型的详细信息，如寄存器布局、异常处理和中断服务例程的编写，这对于开发实时操作系统（RTOS）或编写中断驱动的程序至关重要。此外，还介绍了Cortex-M3的中断系统，包括中断向量表、优先级管理和中断嵌套。对于硬件开发人员，本书讲解了Cortex-M3的系统级设计，包括连接到处理器的外设接口、电源管理、时钟系统和调试选项，如JTAG和SWD（串行线调试）。这些内容有助于读者设计和实现基于Cortex-M3的系统。此外，书中可能还包括了开发工具的使用，如编译器、链接器和调试器，以及如何使用这些工具进行性能分析和优化。对于嵌入式软件开发者，书中可能提供了有关实时编程、内存管理、任务调度以及优化技巧的实践指导。值得注意的是，这本书提醒读者，由于科技的快速发展，书中所包含的信息可能会随时间而过时。因此，实践者和研究人员应当依赖最新的研究、经验和专业实践来更新他们的知识，并且遵循出版商的权限政策，如有需要，应寻求适当的许可来复制或传播书中的内容。 "The definitive guide to the ARM Cortex-M3"是学习和精通ARM Cortex-M3处理器不可或缺的参考资料，无论你是硬件工程师、软件开发者还是嵌入式系统的学生，都能从中受益匪浅。通过阅读这本书，你可以深入了解Cortex-M3的工作原理，提升你的设计和编程能力，从而更好地利用这一强大的微控制器平台。

8 CHAPTER 1 Introduction

one of the instruction sets. The Thumb instruction set provides only a subset of the ARM instructions,

but it can provide higher code density. It is useful for products with tight memory requirements.

As the architecture version has been updated, extra instructions have been added to both ARM

instructions and Thumb instructions. Appendix B provides some information on the change of Thumb

instructions during the architecture enhancements. In 2003, ARM announced the Thumb-2 instruction

set, which is a new superset of Thumb instructions that contains both 16-bit and 32-bit instructions.

The details of the instruction set are provided in a document called The ARM Architecture Reference Man-

ual (also known as the ARM ARM). This manual has been updated for the ARMv5 architecture, the ARMv6

architecture, and the ARMv7 architecture. For the ARMv7 architecture, due to its growth into different pro-

ﬁles, the speciﬁcation is also split into different documents. For the Cortex-M3 instruction set, the complete

details are speciﬁed in the ARM v7-M Architecture Application Level Reference Manual [Ref. 2]. Appendix A

of this book also covers information regarding instruction sets required for software development.

1.4 THE THUMB-2 TECHNOLOGY AND INSTRUCTION

SET ARCHITECTURE

The Thumb-2

technology extended the Thumb Instruction Set Architecture (ISA) into a highly efﬁcient

and powerful instruction set that delivers signiﬁcant beneﬁts in terms of ease of use, code size, and per-

formance (see Figure 1.4). The extended instruction set in Thumb-2 is a superset of the previous 16-bit

Thumb instruction set, with additional 16-bit instructions alongside 32-bit instructions. It allows more

complex operations to be carried out in the Thumb state, thus allowing higher efﬁciency by reducing

the number of states switching between ARM state and Thumb state.

Focused on small memory system devices such as microcontrollers and reducing the size of the proces-

sor, the Cortex-M3 supports only the Thumb-2 (and traditional Thumb) instruction set. Instead of using

ARM instructions for some operations, as in traditional ARM processors, it uses the Thumb-2 instruction

set for all operations. As a result, the Cortex-M3 processor is not backward compatible with traditional

Thumb and Thumb-2 are registered trademarks of ARM.

FIGURE 1.4

The Relationship between the Thumb Instruction Set in Thumb-2 Technology and the Traditional Thumb.

Thumb

instructions

(16 bits)

Thumb-2 technology

32-bit and 16-bit

Thumb instruction set

Cortex-M3

ARMv7-M

architecture

91.5 Cortex-M3 Processor Applications

ARM processors. That is, you cannot run a binary image for ARM7 processors on the Cortex-M3 processor.

Nevertheless, the Cortex-M3 processor can execute almost all the 16-bit Thumb instructions, including all

16-bit Thumb instructions supported on ARM7 family processors, making application porting easy.

With support for both 16-bit and 32-bit instructions in the Thumb-2 instruction set, there is no need

to switch the processor between Thumb state (16-bit instructions) and ARM state (32-bit instructions).

For example, in ARM7 or ARM9 family processors, you might need to switch to ARM state if you want

to carry out complex calculations or a large number of conditional operations and good performance is

needed, whereas in the Cortex-M3 processor, you can mix 32-bit instructions with 16-bit instructions

without switching state, getting high code density and high performance with no extra complexity.

The Thumb-2 instruction set is a very important feature of the ARMv7 architecture. Compared

with the instructions supported on ARM7 family processors (ARMv4T architecture), the Cortex-M3

processor instruction set has a large number of new features. For the ﬁrst time, hardware divide instruc-

tion is available on an ARM processor, and a number of multiply instructions are also available on the

Cortex-M3 processor to improve data-crunching performance. The Cortex-M3 processor also supports

unaligned data accesses, a feature previously available only in high-end processors.

1.5 CORTEX-M3 PROCESSOR APPLICATIONS

With its high performance and high code density and small silicon footprint, the Cortex-M3 processor

is ideal for a wide variety of applications:

• Low-cost microcontrollers: The Cortex-M3 processor is ideally suited for low-cost microcontrollers,

which are commonly used in consumer products, from toys to electrical appliances. It is a highly

competitive market due to the many well-known 8-bit and 16-bit microcontroller products on

the market. Its lower power, high performance, and ease-of-use advantages enable embedded

developers to migrate to 32-bit systems and develop products with the ARM architecture.

• Automotive: Another ideal application for the Cortex-M3 processor is in the automotive industry.

The Cortex-M3 processor has very high-performance efﬁciency and low interrupt latency, allowing

it to be used in real-time systems. The Cortex-M3 processor supports up to 240 external vectored

interrupts, with a built-in interrupt controller with nested interrupt supports and an optional MPU,

making it ideal for highly integrated and cost-sensitive automotive applications.

Data communications• : The processor’s low power and high efﬁciency, coupled with instructions

in Thumb-2 for bit-ﬁeld manipulation, make the Cortex-M3 ideal for many communications

applications, such as Bluetooth and ZigBee.

• Industrial control: In industrial control applications, simplicity, fast response, and reliability are

key factors. Again, the Cortex-M3 processor’s interrupt feature, low interrupt latency, and enhanced

fault-handling features make it a strong candidate in this area.

• Consumer products: In many consumer products, a high-performance microprocessor (or several of

them) is used. The Cortex-M3 processor, being a small processor, is highly efﬁcient and low in power and

supports an MPU enabling complex software to execute while providing robust memory protection.

There are already many Cortex-M3 processor-based products on the market, including low-end

products priced as low as US$1, making the cost of ARM microcontrollers comparable to or lower than

that of many 8-bit microcontrollers.

10 CHAPTER 1 Introduction

1.6 ORGANIZATION OF THIS BOOK

This book contains a general overview of the Cortex-M3 processor, with the rest of the contents divided

into a number of sections:

• Chapters 1 and 2, Introduction and Overview of the Cortex-M3

• Chapters 3 through 6, Cortex-M3 Basics

• Chapters 7 through 9, Exceptions and Interrupts

• Chapters 10 and 11, Cortex-M3 Programming

• Chapters 12 through 14, Cortex-M3 Hardware Features

• Chapters 15 and 16, Debug Supports in Cortex-M3

• Chapters 17 through 21, Application Development with Cortex-M3

Appendices•

1.7 FURTHER READING

This book does not contain all the technical details on the Cortex-M3 processor. It is intended to

be a starter guide for people who are new to the Cortex-M3 processor and a supplemental reference

for people using Cortex-M3 processor-based microcontrollers. To get further detail on the Cortex-M3

processor, the following documents, available from ARM (www.arm.com) and ARM partner web sites,

should cover most necessary details:

• The Cortex-M3 Technical Reference Manual (TRM) [Ref. 1] provides detailed information about

the processor, including programmer’s model, memory map, and instruction timing.

• The ARMv7-M Architecture Application Level Reference Manual [Ref. 2] contains detailed

information about the instruction set and the memory model.

Refer to datasheets for the Cortex-M3 processor-based microcontroller products; visit the manufacturer •

web site for the datasheets on the Cortex-M3 processor-based product you plan to use.

• Cortex-M3 User Guides are available from MCU vendors. In some cases, this user guide is available

as a part of a complete microcontroller product manual. This document contains a programmer’s

model for the ARM Cortex-M3 processor, and instruction set details, and is customized by each

MCU vendors to match their microcontroller implementations.

Refer to • AMBA Speciﬁcation 2.0 [Ref. 4] for more detail regarding internal AMBA interface bus

protocol details.

C programming tips for Cortex-M3 can be found in the • ARM Application Note 179: Cortex-M3

Embedded Software Development [Ref. 7].

This book assumes that you already have some knowledge of and experience with embedded

programming, preferably using ARM processors. If you are a manager or a student who wants to learn

the basics without spending too much time reading the whole book or the TRM, Chapter 2 of this book

is a good one to read because it provides a summary on the Cortex-M3 processor.

CHAPTER

DOI: 10.1016/B978-1-85617-963-8.00005-3

IN THIS CHAPTER

Fundamentals ..........................................................................................................................................11

Registers .................................................................................................................................................12

Operation Modes .....................................................................................................................................14

The Built-In Nested Vectored Interrupt Controller ......................................................................................15

The Memory Map .....................................................................................................................................16

The Bus Interface ....................................................................................................................................17

The MPU .................................................................................................................................................18

The Instruction Set ..................................................................................................................................18

Interrupts and Exceptions .........................................................................................................................19

Debugging Support ................................................................................................................................. 21

Characteristics Summary ........................................................................................................................ 22

Overview of the Cortex-M3

2.1 FUNDAMENTALS

The Cortex™-M3 is a 32-bit microprocessor. It has a 32-bit data path, a 32-bit register bank, and 32-bit

memory interfaces (see Figure 2.1). The processor has a Harvard architecture, which means that it has

a separate instruction bus and data bus. This allows instructions and data accesses to take place at the

same time, and as a result of this, the performance of the processor increases because data accesses do

not affect the instruction pipeline. This feature results in multiple bus interfaces on Cortex-M3, each

with optimized usage and the ability to be used simultaneously. However, the instruction and data

buses share the same memory space (a uniﬁed memory system). In other words, you cannot get 8 GB

of memory space just because you have separate bus interfaces.

For complex applications that require more memory system features, the Cortex-M3 processor has

an optional Memory Protection Unit (MPU), and it is possible to use an external cache if it’s required.

Both little endian and big endian memory systems are supported.

The Cortex-M3 processor includes a number of ﬁxed internal debugging components. These

components provide debugging operation supports and features, such as breakpoints and watchpoints.

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ARM Cortex-M3权威指南：深入解析

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