FT232R USB UART I.C. Datasheet Version 1.04 © Future Technology Devices International Ltd. 2005
Page 6
Serial Interface Engine (SIE) - The Serial Interface Engine (SIE) block performs the Parallel to Serial and Serial to
Parallel conversion of the USB data. In accordance to the USB 2.0 specification, it performs bit stuffing / un-stuffing
and CRC5 / CRC16 generation / checking on the USB data stream.
USB Protocol Engine - The USB Protocol Engine manages the data stream from the device USB control endpoint. It
handles the low level USB protocol (Chapter 9) requests generated by the USB host controller and the commands for
controlling the functional parameters of the UART.
FIFO TX Buffer (128 bytes) - Data from the USB data out endpoint is stored in the FIFO TX buffer and removed from
the buffer to the UART transmit register under control of the UART FIFO controller.
FIFO RX Buffer (256 bytes) - Data from the UART receive register is stored in the FIFO RX buffer prior to being
removed by the SIE on a USB request for data from the device data in endpoint.
UART FIFO Controller - The UART FIFO controller handles the transfer of data between the FIFO RX and TX buffers
and the UART transmit and receive registers.
UART Controller with Programmable Signal Inversion and High Drive - Together with the UART FIFO Controller
the UART Controller handles the transfer of data between the FIFO RX and FIFO TX buffers and the UART transmit
and receive registers. It performs asynchronous 7 / 8 bit Parallel to Serial and Serial to Parallel conversion of the
data on the RS232 (RS422 and RS485) interface. Control signals supported by UART mode include RTS, CTS,
DSR , DTR, DCD and RI. The UART Controller also provides a transmitter enable control signal pin option (TXDEN)
to assist with interfacing to RS485 transceivers. RTS / CTS, DSR / DTR and X-On / X-Off handshaking options are
also supported. Handshaking, where required, is handled in hardware to ensure fast response times. The UART also
supports the RS232 BREAK setting and detection conditions. A new feature, programmable in the internal EEPROM
allows the UART signals to each be individually inverted. Another new EEPROM programmable feature allows a high
signal drive strength to be enabled on the UART interface and CBUS pins.
Baud Rate Generator - The Baud Rate Generator provides a x16 clock input to the UART Controller from the 48MHz
reference clock and consists of a 14 bit prescaler and 3 register bits which provide fine tuning of the baud rate
(used to divide by a number plus a fraction or “sub-integer”). This determines the Baud Rate of the UART, which is
programmable from 183 baud to 3 million baud.
The FT232R supports all standard baud rates and non-standard baud rates from 300 Baud up to 3 Megabaud.
Achievable non-standard baud rates are calculated as follows -
Baud Rate = 3000000 / (n + x)
where n can be any integer between 2 and 16,384 ( = 2
14
) and x can be a sub-integer of the value 0, 0.125, 0.25,
0.375, 0.5, 0.625, 0.75, or 0.875. When n = 1, x = 0, i.e. baud rate divisors with values between 1 and 2 are not
possible.
This gives achievable baud rates in the range 183.1 baud to 3,000,000 baud. When a non-standard baud rate is
required simply pass the required baud rate value to the driver as normal, and the FTDI driver will calculate the
required divisor, and set the baud rate. See FTDI application note AN232B-05 for more details.
RESET Generator - The integrated Reset Generator Cell provides a reliable power-on reset to the device internal
circuitry on power up. A RESET# input pin is provided to allow other devices to reset the FT232R. RESET# can be
tied to VCCIO or left unconnected, unless it is a requirement to reset the device from external logic or an external
reset generator I.C.
Internal EEPROM - The internal EEPROM in the FT232R can be used to store USB Vendor ID (VID), Product ID
(PID), device serial number, product description string, and various other USB configuration descriptors. The internal
EEPROM is also used to configure the CBUS pin functions. The device is supplied with the internal EEPROM settings
preprogrammed as described in Section 10.
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