xilinx简单双口ram的仿真实例

以下是一个简单的Xilinx双口RAM的仿真实例：

1. 创建一个新的VHDL文件，命名为dual_port_ram.vhd。
2. 在文件中添加以下代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity dual_port_ram is
    generic (
        DATA_WIDTH : integer := 8;
        ADDR_WIDTH : integer := 8
    );
    port (
        clk : in std_logic;
        wea : in std_logic;
        addra : in std_logic_vector(ADDR_WIDTH-1 downto 0);
        dina : in std_logic_vector(DATA_WIDTH-1 downto 0);
        rea : in std_logic;
        addrb : in std_logic_vector(ADDR_WIDTH-1 downto 0);
        doutb : out std_logic_vector(DATA_WIDTH-1 downto 0)
    );
end entity dual_port_ram;

architecture Behavioral of dual_port_ram is
    type ram_array is array (2**ADDR_WIDTH-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
    signal ram : ram_array := (others => (others => '0'));
begin
    process (clk)
    begin
        if rising_edge(clk) then
            if wea = '1' then
                ram(to_integer(unsigned(addra))) <= dina;
            end if;
            if rea = '1' then
                doutb <= ram(to_integer(unsigned(addrb)));
            end if;
        end if;
    end process;
end architecture Behavioral;

3. 在Vivado中创建一个新的仿真测试台，命名为dual_port_ram_tb。
4. 添加以下代码以实例化dual_port_ram模块并设置输入和输出：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity dual_port_ram_tb is
end entity dual_port_ram_tb;

architecture Behavioral of dual_port_ram_tb is
    signal clk : std_logic := '0';
    signal wea : std_logic := '0';
    signal addra : std_logic_vector(7 downto 0) := (others => '0');
    signal dina : std_logic_vector(7 downto 0) := (others => '0');
    signal rea : std_logic := '0';
    signal addrb : std_logic_vector(7 downto 0) := (others => '0');
    signal doutb : std_logic_vector(7 downto 0) := (others => '0');
begin
    uut : entity work.dual_port_ram
        generic map (
            DATA_WIDTH => 8,
            ADDR_WIDTH => 8
        )
        port map (
            clk => clk,
            wea => wea,
            addra => addra,
            dina => dina,
            rea => rea,
            addrb => addrb,
            doutb => doutb
        );

    process
    begin
        for i in 0 to 255 loop
            addra <= std_logic_vector(to_unsigned(i, 8));
            dina <= std_logic_vector(to_unsigned(i*2, 8));
            wea <= '1';
            wait for 10 ns;

            addrb <= std_logic_vector(to_unsigned(i, 8));
            rea <= '1';
            wait for 10 ns;

            assert doutb = std_logic_vector(to_unsigned(i*2, 8))
                report "Error: Expected " & integer'image(i*2) & ", got " & integer'image(to_integer(unsigned(doutb))) severity error;

            rea <= '0';
            wea <= '0';
            wait for 10 ns;
        end loop;

        wait;
    end process;

    process
    begin
        while true loop
            clk <= '0';
            wait for 5 ns;
            clk <= '1';
            wait for 5 ns;
        end loop;
    end process;
end architecture Behavioral;

5. 运行仿真测试台并查看输出结果，如果没有错误，则说明双口RAM的仿真测试通过。