用vivado编写test 测试以上代码

以下是一个可能的测试代码示例，您可以根据自己的代码进行修改：

`timescale 1ns / 1ps

module test;

reg rst;
reg clk;
wire [5:0] count60;
wire [6:0] count100;

// Instantiate the modules
Count60 count60_inst(
    .clk(clk),
    .rst(rst),
    .count(count60)
);

Count100 count100_inst(
    .clk(clk),
    .rst(rst),
    .count(count100)
);

Clk_100Hz clk_100Hz_inst(
    .clk(clk_100Hz),
    .rst(rst)
);

initial begin
    // Initialize inputs
    rst = 1;
    clk = 0;
    
    // Wait for a few clock cycles
    #10;
    
    // Deassert reset
    rst = 0;
    
    // Wait for 60 seconds
    #60000000;
    
    // Assert reset
    rst = 1;
    
    // Wait for a few clock cycles
    #10;
    
    // Check the output of the counters
    $display("Count60: %d", count60);
    $display("Count100: %d", count100);
end

endmodule

请注意，这只是一个示例测试代码，具体实现方式可能因您的代码而异。