module test; typedef struct packed { logic [9:-1][2:0] a; //REQ-EXT-10001, REQ-EXT-10004 } ST1; typedef struct { ST1 st1; logic [2:0] b; } ST2; typedef struct { logic [31:0] c; } ST3; typedef struct { ST3 st3; ST2 st2_arr[3:0]; } ST4; initial begin ST2 st2; ST2 st2_1 = (3'b101, {ST1{10'b110}}, {ST1{20'b10101010101010}},{ST1{30'b1}}); ST2 st2_2 = (3'b010, {ST1{10'b101}}, {ST1{20'b01010101010101}},{ST1{30'b0}}); st2 = (2'b01, {3'b1, 3'b0, 12'b1}); $display("%p",st2); //CHECK-001:'{a:'h1}, st2:'{'a:'h1}, '{a:'h0},'{a:h1}}} $display("st2_1:%p", st2_1); //CHECK-002 $display("st2_2:%p", st2_2); //CHECK-003 end endmodule when compiled by vcs, it says following verilog source has syntax error: "sc_assignment_pattern_035.sv",35: token is ',' ST2 st2_1 = (3'b101, {ST1{10'b110}}, {ST1{20'b1010101010}},{ST1{30'b1}}); //REQ-EXT-10201 1 error, how should I fix this syntax error? help me and thanks a lot!

The syntax error is caused by the extra "0" in the 20-bit binary value in the initialization of ST2 structure. It should be 20'b1010101010101010 instead of 20'b1010101010. The correct code should be:

ST2 st2_1 = (3'b101, {ST1{10'b110}}, {ST1{20'b1010101010101010}},{ST1{30'b1}});

After fixing this, the code should compile without any syntax error.

相关问题

module test; typedef struct packed { logic [9:-1][2:0] a; //REQ-EXT-10001, REQ-EXT-10004 }ST1; typedef struct { ST1 st1; ST2 st2[2:0]; }ST2; initial begin ST2 st2; st2='{2'b01, '{3'b1, 3'b0, 12'b1}}; //REQ-EXT-10101 &display("%p", st2); //CHECK-001: '{st1:'{a:'h1}, st2:"{'{a:'h1},'{a:'h0},'{a:'h1}}} end endmodule REQ-EXT-10101处可以如何修改，使得代码仍然可以跑通呢？

在 REQ-EXT-10101 处，可以将赋值语句修改为以下两种方式之一：

1. 使用大括号初始化整个结构体：

st2 = '{ {10'h1}, '{3'b1, 3'b0, 12'h1} };

2. 逐个初始化结构体成员：

st2.st1.a = '{10'h1};
st2.st2[0].a = '{3'b1, 3'b0, 12'h1};
st2.st2[1].a = '{3'b1, 3'b0, 12'h1};
st2.st2[2].a = '{3'b1, 3'b0, 12'h1};

修改后的完整代码如下：

module test;
  typedef struct packed {
    logic [9:-1][2:0] a; //REQ-EXT-10001, REQ-EXT-10004
  } ST1;

  typedef struct {
    ST1 st1;
    ST2 st2[2:0];
  } ST2;

  initial begin
    ST2 st2;
    // 使用大括号初始化整个结构体
    st2 = '{ {10'h1}, '{3'b1, 3'b0, 12'h1} };
    $display("%p", st2); //CHECK-001: '{st1:'{a:'h1}, st2:"{'{a:'h1},'{a:'h0},'{a:'h1}}}
  end
endmodule

module test; typedef struct packed { logic [9:-1][2:0] a; ///REQ-EXT-10001, REQ-EXT-10004 } ST1; typedef struct packed { logic [2:0] b; } ST2; typedef struct { ST1 st1; ST2 st2[2:0]; }ST3; initial begin ST2 st2 ='{'{'{a:'h1, st1:'{'{b:'h2}}}, '{a:'h0, st1:'{'{b:'h1}}}, '{a:'h1,st1:'{'{b:h0}}}}; $display("%p", st2); end endmodule seems there is error with the initailization of st2, how should I modify the code so that it can be compiled successfully with vcs?

The initialization of st2 is incorrect. You can modify the code as follows to initialize st2 correctly:

ST2 st2[3] = '{'{3'h2}, '{3'h1}, '{3'h0}};

This initializes st2 as an array of three elements, each element being an instance of ST2 initialized with the values 3'h2, 3'h1, and 3'h0 respectively. Note that the '{' and '}' characters are used for concatenation of elements in the array.