写一个jk触发器的VHDL程序

JK触发器是一种双稳态触发器，它由两个输入J（Set）和K（Reset）控制其状态。当J为高电平并且K为低电平时，触发器从当前状态翻转到另一个状态。下面是一个简单的VHDL（Verilog Hardware Description Language）程序，用于描述JK触发器的基本结构：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity JKTrigger is
    Port ( J : in STD_LOGIC;      -- Set input
           K : in STD_LOGIC;      -- Reset input
           Q : out STD_LOGIC);     -- Output stored state
end JKTrigger;

architecture Behavioral of JKTrigger is
begin
    process(J, K)
    begin
        if rising_edge(J) and not K then
            Q <= '1'; -- Flip-flop changes to high state when J is high and K is low
        elsif K = '1' then
            Q <= '0'; -- Reset to low state when K is high
        else
            Q <= Q;   -- Hold the current state otherwise
        end if;
    end process;
end Behavioral;

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