用 VHDL 语言分别编写一个 D 触发器和 JK 触发器

以下是 VHDL 代码实现：

D 触发器：

library ieee;
use ieee.std_logic_1164.all;

entity d_ff is
    port (
        clk : in std_logic;
        d   : in std_logic;
        q   : out std_logic
    );
end entity d_ff;

architecture behavioral of d_ff is
begin
    process(clk)
    begin
        if rising_edge(clk) then
            q <= d;
        end if;
    end process;
end architecture behavioral;

JK 触发器：

library ieee;
use ieee.std_logic_1164.all;

entity jk_ff is
    port (
        clk : in std_logic;
        j   : in std_logic;
        k   : in std_logic;
        q   : out std_logic
    );
end entity jk_ff;

architecture behavioral of jk_ff is
    signal q_int : std_logic;
begin
    process(clk)
    begin
        if rising_edge(clk) then
            if j = '1' and k = '0' then
                q_int <= '1';
            elsif j = '0' and k = '1' then
                q_int <= '0';
            elsif j = '1' and k = '1' then
                q_int <= not q_int;
            end if;
        end if;
    end process;

    q <= q_int;
end architecture behavioral;