用Verilog写一个axi协议

以下是一个简单的 AXI 协议的 Verilog 示例代码，仅供参考：

module axi(
    input  clk,
    input  resetn,
    input  [31:0] awaddr,
    input  [2:0]  awprot,
    input  [3:0]  awsize,
    input  [1:0]  awburst,
    input  [3:0]  awlen,
    input  [31:0] wdata,
    input  [3:0]  wstrb,
    input  [1:0]  wlast,
    input  [31:0] araddr,
    input  [2:0]  arprot,
    input  [3:0]  arsize,
    input  [1:0]  arburst,
    input  [3:0]  arlen,
    output [1:0]  rresp,
    output [31:0] rdata,
    output [1:0]  rlast,
    output        rvalid,
    output        rready,
    output [1:0]  bresp,
    output        bvalid,
    output        bready
);

// AXI Master Write FSM states
parameter IDLE = 2'b00;
parameter AWAIT = 2'b01;
parameter WDATA = 2'b10;
parameter BRESP = 2'b11;

// AXI Slave Read FSM states
parameter RREADY = 2'b00;
parameter RVALID = 2'b01;
parameter RRESP = 2'b10;

// AXI Slave Write FSM states
parameter BREADY = 2'b00;
parameter BVALID = 2'b01;

// AXI Master Write FSM
reg [1:0] aw_state = IDLE;
reg [31:0] awaddr_reg;
reg [3:0] awlen_reg;
reg [3:0] wlen_reg;
reg [31:0] wdata_reg;
reg [3:0] wstrb_reg;
reg [1:0] wlast_reg;
reg [1:0] bresp_reg;
reg [1:0] bresp_next;
reg bvalid_reg;

// AXI Slave Read FSM
reg [1:0] ar_state = RREADY;
reg [3:0] arlen_reg;
reg [31:0] araddr_reg;
reg [1:0] rresp_reg;
reg [31:0] rdata_reg;
reg [1:0] rlast_reg;
reg rvalid_reg;

// AXI Slave Write FSM
reg [1:0] b_state = BREADY;
reg [1:0] bresp_reg;
reg [1:0] bresp_next;
reg bvalid_reg;

// AXI Master Write FSM
always @(posedge clk) begin
    if(!resetn) begin
        aw_state <= IDLE;
        awaddr_reg <= 0;
        awlen_reg <= 0;
        wlen_reg <= 0;
        wdata_reg <= 0;
        wstrb_reg <= 0;
        wlast_reg <= 0;
        bresp_reg <= 0;
        bvalid_reg <= 0;
    end
    else begin
        case(aw_state)
            IDLE: begin
                if(awburst[1:0] == 2'b01) begin
                    aw_state <= AWAIT;
                    awaddr_reg <= awaddr;
                    awlen_reg <= awlen;
                end
                else begin
                    awaddr_reg <= awaddr;
                    aw_state <= WDATA;
                end
            end
            AWAIT: begin
                if(wlen_reg == awlen_reg) begin
                    aw_state <= BRESP;
                end
                else begin
                    aw_state <= WDATA;
                end
            end
            WDATA: begin
                wlen_reg <= wlen_reg + 1;
                wdata_reg <= wdata;
                wstrb_reg <= wstrb;
                wlast_reg <= wlast;
                if(wlen_reg == awlen_reg) begin
                    aw_state <= BRESP;
                end
                else begin
                    awaddr_reg <= awaddr_reg + 4;
                end
            end
            BRESP: begin
                bresp_reg <= bresp_next;
                bvalid_reg <= 1;
                aw_state <= IDLE;
            end
        endcase
    end
end

// AXI Slave Read FSM
always @(posedge clk) begin
    if(!resetn) begin
        ar_state <= RREADY;
        arlen_reg <= 0;
        araddr_reg <= 0;
        rresp_reg <= 0;
        rdata_reg <= 0;
        rlast_reg <= 0;
        rvalid_reg <= 0;
    end
    else begin
        case(ar_state)
            RREADY: begin
                if(arburst[1:0] == 2'b01) begin
                    ar_state <= RVALID;
                    arlen_reg <= arlen;
                    araddr_reg <= araddr;
                end
            end
            RVALID: begin
                rdata_reg <= araddr_reg;
                rlast_reg <= (arlen_reg == 0);
                rresp_reg <= 0;
                rvalid_reg <= 1;
                if(rlast_reg) begin
                    ar_state <= RREADY;
                end
                else begin
                    arlen_reg <= arlen_reg - 1;
                    araddr_reg <= araddr_reg + 4;
                end
            end
        endcase
    end
end

// AXI Slave Write FSM
always @(posedge clk) begin
    if(!resetn) begin
        b_state <= BREADY;
        bresp_reg <= 0;
        bvalid_reg <= 0;
    end
    else begin
        case(b_state)
            BREADY: begin
                if(wlast_reg) begin
                    b_state <= BVALID;
                    bresp_next <= 0;
                end
            end
            BVALID: begin
                bresp_reg <= bresp_next;
                bvalid_reg <= 1;
                if(bvalid && bready) begin
                    b_state <= BREADY;
                end
            end
        endcase
    end
end

// AXI Master Write interface
assign awready = (aw_state == AWAIT) ? 1 : 0;
assign wready = (aw_state == WDATA) ? 1 : 0;
assign bresp = bresp_reg;
assign bvalid = bvalid_reg;

// AXI Slave Read interface
assign rdata = rdata_reg;
assign rlast = rlast_reg;
assign rresp = rresp_reg;
assign rvalid = rvalid_reg;

// AXI Slave Write interface
assign bready = (b_state == BREADY) ? 1 : 0;

endmodule

需要注意的是，这只是一个简单的示例，实际开发中可能需要根据具体的应用场景进行修改和扩展。同时，还需要注意 AXI 协议的细节和规范，以保证与其他设备和系统的兼容性。