用Case when语句完成四选一多路选择器的VHDL语句仿真

在 VHDL（VHSIC Hardware Description Language）设计语言中，`CASE WHEN` 语句类似于其他编程语言中的条件语句，用于实现多路分支的选择结构，可以用来构建四选一（4-to-1）多路选择器。多路选择器是一种数字电路，它根据输入信号的不同组合，从四个输入信号中选择并输出其中一个。

下面是一个简单的 VHDL 示例，展示如何使用 `CASE` 结构来实现一个4-to-1多路选择器：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FourToOneSelector is
   Port ( A : in STD_LOGIC; -- Input signals
          B : in STD_LOGIC;
          C : in STD_LOGIC;
          D : in STD_LOGIC;
          Output : out STD_LOGIC); -- Output signal
end FourToOneSelector;

architecture Behavioral of FourToOneSelector is
begin
   Process (A, B, C, D)
      variable Selection : STD_LOGIC := '0'; -- Default output value
   begin
      case (A & B & C) is -- Multiple conditions for the four possible inputs
         when "000" => Selection <= D; -- Connects to D if all inputs are 0
         when "001" => Selection <= C; -- Connects to C if A is 0 and others are 1
         when "010" => Selection <= B; -- Connects to B if B is 0 and others are 1
         when "1XX" => Selection <= A; -- Connects to A if both A and other two are 1
         when others => Selection <= 'X'; -- Unspecified input combination, usually an error
      end case;

      Output <= Selection; -- Assign the selected value to the output
   end process;
end Behavioral;

在这个例子中，`Selection` 变量会根据 `A`, `B`, 和 `C` 的输入状态动态变化，并将结果赋值给 `Output`。如果输入组合不符合上述情况（如所有输入都是0），则表示未定义或错误，通常输出 `'X'` 表示。