stm32 adc 采集频率

根据引用\[2\]中的信息，如果将PLCK2设置为8分频，那么ADCCLK为9MHz。在外部晶振为8MHz的情况下，这是STM32F103系列ADC能够获得的最低时钟频率。根据引用\[3\]中的信息，STM32 ADC是一个12位精度的模拟数字转换器。根据引用\[2\]中的信息，最大采样周期为252个周期。因此，最大采样频率为9MHz/252周期，约为35.7kHz。这意味着在1秒钟内，STM32F1系列的ADC最多可以采样35.7k个数据。
#### 引用[.reference_title]
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