verilog代码实现：序列检测器，当输入010时开始输出序列，当输入101时停止输出序列。

下面是一个简单的 Verilog 实现，实现了一个输入为 010 时开始输出序列，输入为 101 时停止输出序列的序列检测器。

module sequence_detector(
    input clk,
    input reset,
    input data_in,
    output reg data_out
);

// 定义状态
localparam IDLE = 2'b00;
localparam DETECTING = 2'b01;
localparam OUTPUTTING = 2'b10;

// 定义当前状态和下一个状态
reg [1:0] state, next_state;

// 初始状态为 IDLE
initial begin
    state = IDLE;
end

// 状态转移逻辑
always @(posedge clk, posedge reset) begin
    if (reset) begin
        state <= IDLE;
    end else begin
        state <= next_state;
    end
end

// 状态机逻辑
always @(*) begin
    case (state)
        IDLE: begin
            if (data_in == 1'b0) begin
                next_state = DETECTING;
            end else begin
                next_state = IDLE;
            end
        end
        DETECTING: begin
            if (data_in == 1'b1) begin
                next_state = OUTPUTTING;
            end else begin
                next_state = DETECTING;
            end
        end
        OUTPUTTING: begin
            if (data_in == 1'b0) begin
                next_state = DETECTING;
            end else begin
                next_state = IDLE;
            end
        end
    endcase
end

// 输出逻辑
always @(posedge clk, posedge reset) begin
    if (reset) begin
        data_out <= 1'b0;
    end else begin
        case (state)
            IDLE: begin
                data_out <= 1'b0;
            end
            DETECTING: begin
                data_out <= 1'b0;
            end
            OUTPUTTING: begin
                data_out <= 1'b1;
            end
        endcase
    end
end

endmodule

在该代码中，我们定义了三个状态：IDLE，DETECTING 和 OUTPUTTING。当输入为 010 时，状态从 IDLE 切换到 DETECTING，当输入为 101 时，状态从 OUTPUTTING 切换到 IDLE。在 OUTPUTTING 状态下，我们输出序列。