uart串口通信verilog代码

下面是一个简单的 UART 串口通信的 Verilog 代码示例：

module uart(
    input clk, // 时钟信号
    input reset, // 复位信号
    input rx, // 接收端口
    output tx // 发送端口
);

// 定义波特率
parameter BAUD_RATE = 9600;

// 定义计数器的位宽
parameter COUNTER_WIDTH = $clog2(2 * BAUD_RATE);

// 定义状态机的状态
typedef enum logic [1:0] {
    IDLE,
    START,
    DATA,
    STOP
} state_t;

// 定义状态机的当前状态和计数器
reg [1:0] state = IDLE;
reg [COUNTER_WIDTH-1:0] counter = 0;

// 定义缓冲区和缓冲区指针
reg [7:0] buffer = 0;
reg [3:0] buffer_ptr = 0;

// 定义发送数据的标志位
reg send = 0;

// 接收数据
always @(posedge clk) begin
    if (reset) begin
        state <= IDLE;
        counter <= 0;
        buffer <= 0;
        buffer_ptr <= 0;
        send <= 0;
    end else begin
        case (state)
            IDLE: begin
                buffer <= 0;
                buffer_ptr <= 0;
                send <= 0;
                if (!rx) begin
                    state <= START;
                    counter <= 0;
                end
            end
            
            START: begin
                if (counter == COUNTER_WIDTH-1) begin
                    state <= DATA;
                    counter <= 0;
                end else begin
                    counter <= counter + 1;
                end
            end
            
            DATA: begin
                if (counter == COUNTER_WIDTH-1) begin
                    buffer[buffer_ptr] <= rx;
                    buffer_ptr <= buffer_ptr + 1;
                    if (buffer_ptr == 7) begin
                        state <= STOP;
                        counter <= 0;
                    end else begin
                        counter <= 0;
                    end
                end else begin
                    counter <= counter + 1;
                end
            end
            
            STOP: begin
                if (counter == COUNTER_WIDTH-1) begin
                    state <= IDLE;
                    counter <= 0;
                    send <= 1;
                end else begin
                    counter <= counter + 1;
                end
            end
            
            default: state <= IDLE;
        endcase
    end
end

// 发送数据
always @(posedge clk) begin
    if (reset) begin
        tx <= 1;
    end else if (send) begin
        tx <= 0;
        send <= 0;
    end else begin
        tx <= 1;
    end
end

endmodule

这个代码实现了一个简单的串口通信模块，可以接收来自 rx 端口的数据并将其发送到缓冲区中，然后再将缓冲区中的数据发送到 tx 端口中。你可以根据需要进行修改和优化。