试设计一个2线-4线的二进制代码译码器,输入 0 0 为什么 输出是0111
时间: 2024-02-29 13:57:11 浏览: 20
根据2线-4线的二进制代码译码器的逻辑,输入的两位二进制数可以对应4个输出之一。对于输入 0 0,根据2线-4线的译码表格,对应的输出应该是0111。
以下是对应的真值表:
| A | B | Y0 | Y1 | Y2 | Y3 |
|---|---|----|----|----|----|
| 0 | 0 | 1 | 1 | 1 | 0 |
| 0 | 1 | 1 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 | 1 | 1 |
因此,输入 0 0 的输出应该是 0111。
相关问题
2线-4线的二进制代码译码器 的真值表
2线-4线的二进制代码译码器可将输入的两位二进制代码转换为四个输出信号之一,其真值表如下:
| 输入 | 输出 |
|------|------|
| 00 | 0001 |
| 01 | 0010 |
| 10 | 0100 |
| 11 | 1000 |
其中,输入列的第一位为最高位,第二位为最低位;输出列的第一位对应数码 0,第二位对应数码 1,以此类推,即输出列从左至右的位数对应数码 0、1、2、3。例如,当输入为 01 时,输出为 0010,表示数码 1。
用vhdl语言编写一个将二进制码转换成 0-E 的七段码译码器
好的,我可以为您编写一个简单的七段码译码器的VHDL代码,将二进制码转换为0-E的七段码。以下是代码:
```vhdl
entity binary_to_7seg is
Port ( bin : in STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (6 downto 0));
end binary_to_7seg;
architecture Behavioral of binary_to_7seg is
begin
process(bin)
begin
case bin is
when "0000" => seg <= "1000000"; -- 0
when "0001" => seg <= "1111001"; -- 1
when "0010" => seg <= "0100100"; -- 2
when "0011" => seg <= "0110000"; -- 3
when "0100" => seg <= "0011001"; -- 4
when "0101" => seg <= "0010010"; -- 5
when "0110" => seg <= "0000010"; -- 6
when "0111" => seg <= "1111000"; -- 7
when "1000" => seg <= "0000000"; -- 8
when "1001" => seg <= "0011000"; -- 9
when "1010" => seg <= "0001000"; -- A
when "1011" => seg <= "0000011"; -- b
when "1100" => seg <= "1000110"; -- C
when "1101" => seg <= "0100001"; -- d
when "1110" => seg <= "0000110"; -- E
when "1111" => seg <= "0001110"; -- F
when others => seg <= "-------"; -- invalid input
end case;
end process;
end Behavioral;
```
这个代码的输入是一个4位的二进制码,输出是一个7位的七段码。当输入的二进制码不是0-F之间的值时,输出将为"-------",表示无效输入。