分别编写一个异步串行口发送程序uart_tx和一个异步串行口接收程序uart_rx，编写testbench将并行数据通过uart_tx传送到uart_rx，用modelsim仿真验证程序的正确性。

在VHDL设计语言中，异步串行口发送程序（uart_tx）通常会包含三个关键部分：发送缓冲区、移位寄存器以及波特率生成器。以下是一个简化版的uart_tx模块示例：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity uart_tx is
    Port (
        data_in : in std_logic_vector(7 downto 0);
        clk     : in std_logic;
        tx      : out std_logic
    );
end uart_tx;

architecture Behavioral of uart_tx is
begin
    process(data_in, clk)
    begin
        if rising_edge(clk) then
            if (data_in = "00000000") then -- 发送结束标志
                tx <= '1';
            else
                tx <= data_in(0); -- 发送当前位
            end if;
        end if;
    end process;
end Behavioral;

异步串行口接收程序（uart_rx）则需要一个同步接收移位寄存器和状态机来检测开始和停止位，并存储接收到的数据。这里同样给出一个简化的例子：

entity uart_rx is
    Port (
        rx      : in std_logic;
        clk     : in std_logic;
        data_out : out std_logic_vector(7 downto 0)
    );
end uart_rx;

architecture Behavioral of uart_rx is
begin
    received_data : std_logic_vector(7 downto 0) := (others => '0');
    receive_state : integer range 0 to 3 := 0; -- 初始化为等待开始位

    process(rx, clk)
    begin
        case receive_state is
            when 0 =>
                if (rx = '1') then
                    receive_state := 1;
                end if;
            when 1 =>
                if (rx = '0') then
                    received_data := received_data & '0';
                elsif (rx = '1') then
                    receive_state := 2;
                end if;
            when 2 =>
                if (rx = '0') then
                    received_data := received_data & '0';
                elsif (rx = '1') then
                    receive_state := 3;
                end if;
            when 3 =>
                if (rx = '1') then
                    receive_state := 0;
                    data_out <= received_data;
                end if;
            when others =>
                -- 处理错误状态...
        end case;
    end process;
end Behavioral;

为了测试这两个功能，你可以创建一个名为`testbench.vhd`的文件，在其中模拟并行数据源、两个UART端口通信，并验证数据是否正确传输。以下是testbench的大致结构：

entity testbench is
    -- ...
end testbench;

architecture Test of testbench is
    signal clk     : std_logic := '0';
    signal data_in : std_logic_vector(7 downto 0);
    signal data_out : std_logic_vector(7 downto 0);

    -- 实例化并配置uart_tx和uart_rx
    -- ...

begin
    -- 序列信号生成器（如：八进制数转换）
    data_gen_process : process
    begin
        -- 发送并行数据到uart_tx
        -- ...
        wait for 5 ns; -- 模拟时间间隔
    end process;

    -- 进行模型仿真
    UUT_process : process(clk)
    begin
        if rising_edge(clk) then
            -- 更新testbench端口
            -- ...
        end if;
    end process;

    -- 验证数据是否正确接收
    assert (data_out = expected_output) report
        "Received data does not match expected output" severity failure;
end Test;