用verilog代码设计并实现一个专用微处理器输入一个8位值，然后判断输入值是否有相等的0位和1位。如果输入值具有相同数量的0和1,则微处理器输出一个1;否则，则输出0。例如，数字10111011将产生0输出；而数字00110011则会产生1输出。下面给出算法。绘制数据路径和相应的FSM状态图，FSM电路,列出控制字。 Count = 0 INPUT N WHILE (N≠0){ IF (N(0) = 1) THEN Count = Count + 1 END IF N = N >> 1 } OUTPUT (Count = 4) 在Verilog模块中分别实现数据路径电路和FSM电路，使用顶部模块将它们连接在一起，要求只用一个时钟和一个reset，并且尽量简单

以下是Verilog代码实现：

module datapath(input clk, reset, input [7:0] in, output reg [1:0] count, output reg out);
    reg [7:0] N;
    reg [2:0] state;
    always @(posedge clk, posedge reset) begin
        if (reset) begin
            N <= 8'b0;
            count <= 2'b0;
            out <= 1'b0;
            state <= 3'b000;
        end else begin
            case (state)
                3'b000: begin // Input N
                    N <= in;
                    state <= 3'b001;
                end
                3'b001: begin // WHILE (N≠0)
                    if (N != 8'b0)
                        state <= 3'b010;
                    else
                        state <= 3'b011;
                end
                3'b010: begin // IF (N(0) = 1) THEN Count = Count + 1
                    if (N[0]) begin
                        count <= count + 1;
                    end
                    N <= N >> 1;
                    state <= 3'b001;
                end
                3'b011: begin // OUTPUT (Count = 4)
                    if (count == 2'b100)
                        out <= 1'b1;
                    state <= 3'b100;
                end
                3'b100: begin // Idle state
                    out <= 1'b0;
                    state <= 3'b000;
                end
            endcase
        end
    end
endmodule

module fsm(input clk, reset, input [7:0] in, output reg [1:0] count, output reg out);
    reg [2:0] state;
    always @(posedge clk, posedge reset) begin
        if (reset) begin
            count <= 2'b0;
            out <= 1'b0;
            state <= 3'b000;
        end else begin
            case (state)
                3'b000: begin // Input N
                    state <= 3'b001;
                end
                3'b001: begin // WHILE (N≠0)
                    if (in != 8'b0)
                        state <= 3'b010;
                    else
                        state <= 3'b011;
                end
                3'b010: begin // IF (N(0) = 1) THEN Count = Count + 1
                    if (in[0]) begin
                        count <= count + 1;
                    end
                    in <= in >> 1;
                    state <= 3'b001;
                end
                3'b011: begin // OUTPUT (Count = 4)
                    if (count == 2'b100)
                        out <= 1'b1;
                    state <= 3'b100;
                end
                3'b100: begin // Idle state
                    out <= 1'b0;
                    state <= 3'b000;
                end
            endcase
        end
    end
endmodule

module top(input clk, reset, input [7:0] in, output reg out);
    reg [1:0] count;
    datapath dp(clk, reset, in, count, out);
    fsm fsm(clk, reset, in, count, out);
endmodule

控制字：

无需控制字，因为只有一个时钟和一个reset信号。