用system verilog写一个预读的异步fifo代码

以下是使用SystemVerilog编写的预读异步FIFO代码：

module async_fifo
#(parameter WIDTH = 8, // 数据宽度
DEPTH = 4, // FIFO深度
PRE_READ = 1) // 预读数目
(input clk, // 时钟信号
input rst, // 复位信号
input wr_en, // 写使能信号
input rd_en, // 读使能信号
input [WIDTH-1:0] data_in, // 输入数据
output logic [WIDTH-1:0] data_out, // 输出数据
output logic full, // FIFO满标志
output logic empty); // FIFO空标志

// 内部信号定义
logic [WIDTH-1:0] fifo [0:DEPTH-1];
logic [$clog2(DEPTH)+1:0] wr_ptr, rd_ptr;
logic [$clog2(DEPTH)+1:0] next_wr_ptr, next_rd_ptr;
logic [$clog2(DEPTH)+1:0] pre_rd_ptr;
logic [$clog2(DEPTH)+1:0] count;

// 初始化
initial begin
wr_ptr <= 'd0;
rd_ptr <= 'd0;
pre_rd_ptr <= 'd0;
count <= 'd0;
end

// 写指针逻辑
always_ff @(posedge clk or negedge rst) begin
if (!rst) begin
wr_ptr <= 'd0;
next_wr_ptr <= 'd0;
end else begin
if (wr_en && !full) begin
next_wr_ptr <= wr_ptr + 1;
end else begin
next_wr_ptr <= wr_ptr;
end
wr_ptr <= next_wr_ptr;
end
end

// 读指针逻辑
always_ff @(posedge clk or negedge rst) begin
if (!rst) begin
rd_ptr <= 'd0;
next_rd_ptr <= 'd0;
end else begin
if (rd_en && !empty) begin
next_rd_ptr <= rd_ptr + 1;
end else begin
next_rd_ptr <= rd_ptr;
end
rd_ptr <= next_rd_ptr;
end
end

// 预读指针逻辑
always_ff @(posedge clk or negedge rst) begin
if (!rst) begin
pre_rd_ptr <= 'd0;
end else begin
if (rd_en && !empty) begin
if (pre_rd_ptr == rd_ptr) begin
pre_rd_ptr <= next_rd_ptr;
end
end else begin
pre_rd_ptr <= rd_ptr;
end
end
end

// 计数器逻辑
always_comb begin
count = (wr_ptr - rd_ptr >= 0) ? wr_ptr - rd_ptr : (DEPTH + wr_ptr - rd_ptr);
end

// 数据写入逻辑
always_ff @(posedge clk or negedge rst) begin
if (!rst) begin
// 初始化
for (integer i = 0; i < DEPTH; i++) begin
fifo[i] <= 'd0;
end
end else begin
// 写入数据
if (wr_en && !full) begin
fifo[wr_ptr] <= data_in;
end
end
end

// 数据输出逻辑
always_comb begin
if (count == 0) begin
empty = 1;
end else begin
empty = 0;
end

if (count == DEPTH) begin
full = 1;
end else begin
full = 0;
end

if (count > PRE_READ) begin
data_out = fifo[pre_rd_ptr];
end
end

endmodule