QuartusVHDL数字钟代码

以下是一个简单的 VHDL 数字钟代码，使用 Quartus II 开发：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity clock is
    port(
        clk: in std_logic;
        reset: in std_logic;
        hours: out std_logic_vector(3 downto 0);
        minutes: out std_logic_vector(5 downto 0);
        seconds: out std_logic_vector(5 downto 0)
    );
end entity;

architecture Behavioral of clock is

    signal cnt: integer range 0 to 1000000 := 0; -- 1 MHz counter
    signal sec_cnt: integer range 0 to 59 := 0; -- seconds counter
    signal min_cnt: integer range 0 to 59 := 0; -- minutes counter
    signal hr_cnt: integer range 0 to 23 := 0; -- hours counter

begin

    process(clk, reset)
    begin
        if (reset = '1') then
            cnt <= 0;
            sec_cnt <= 0;
            min_cnt <= 0;
            hr_cnt <= 0;
        elsif rising_edge(clk) then
            cnt <= cnt + 1;
            if (cnt = 1000000) then -- 1 second has passed
                cnt <= 0;
                sec_cnt <= sec_cnt + 1;
                if (sec_cnt = 60) then -- 1 minute has passed
                    sec_cnt <= 0;
                    min_cnt <= min_cnt + 1;
                    if (min_cnt = 60) then -- 1 hour has passed
                        min_cnt <= 0;
                        hr_cnt <= hr_cnt + 1;
                        if (hr_cnt = 24) then -- reset to 0 after 24 hours
                            hr_cnt <= 0;
                        end if;
                    end if;
                end if;
            end if;
        end if;
    end process;

    -- Convert counters to BCD and output to LEDs
    hours <= std_logic_vector(to_bcd(unsigned(hr_cnt)));
    minutes <= std_logic_vector(to_bcd(unsigned(min_cnt)));
    seconds <= std_logic_vector(to_bcd(unsigned(sec_cnt)));

end architecture;

这个代码定义了一个名为 "clock" 的实体，具有输入时钟信号、复位信号和输出小时、分钟和秒的信号。内部使用四个计数器来跟踪时间，并在每个计数器达到相应的最大值时递增下一个计数器。然后，将计数器转换为 BCD 格式并将其输出到时钟的 LED 显示。