分别编写一个并-串转换程序p2s和一个串-并转换程序s2p，编写testbench将并行数据通过并-串转换程序转换成串行数据，再通过串并转换程序转换成并行数据，用modelsim仿真验证程序的正确性。

在VHDL或Verilog等硬件描述语言中，编写并-串（Parallel to Serial, P2S）和串-并（Serial to Parallel, S2P）转换器通常涉及到同步移位寄存器的设计。这里是一个简化版的伪代码示例：

**并-串转换器 (P2S):**

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity p2s is
    Port (
        clk : in STD_LOGIC; -- 时钟信号
        din : in std_logic_vector(7 downto 0); -- 并行输入数据
        dout : out std_logic; -- 串行输出数据
        empty : out std_logic -- 输出空闲标志
    );
end p2s;

architecture Behavioral of p2s is
begin
    process(clk)
    begin
        if rising_edge(clk) then
            ifdin /= din(Signal-Length - 1 downto 0) then
                dout <= din(0);
                empty <= '0';
            else
                empty <= '1';
            end if;
        end if;
    end process;
end Behavioral;

**串-并转换器 (S2P):**

entity s2p is
    Port (
        clk : in STD_LOGIC; -- 时钟信号
        din : in std_logic; -- 串行输入数据
        dout : out std_logic_vector(7 downto 0); -- 并行输出数据
        empty : in std_logic -- 输入空闲标志
    );
end s2p;

architecture Behavioral of s2p is
    signal data_reg : std_logic_vector(7 downto 0) := (others => 'Z'); -- 移位寄存器
begin
    process(clk, empty)
    begin
        if rising_edge(clk) and empty = '0' then
            data_reg <= data_reg(signed(din));
        end if;
        
        dout <= data_reg;
    end process;
end Behavioral;

**TestBench:**

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_p2s_s2p is
end tb_p2s_s2p;

architecture TB of tb_p2s_s2p is
component p2s is ... end component;
component s2p is ... end component;

signal clk : std_logic := '0'; -- 时钟信号
signal din, dout_s2p, expected_dout_p2s : std_logic_vector(7 downto 0); -- 数据信号

begin
    U1: p2s port map (clk => clk, din => din, dout => dout_s2p, empty => empty_out);
    U2: s2p port map (clk => clk, din => dout_s2p, dout => expected_dout_p2s, empty => empty_in);

    -- 测试用例
    for i in 0 to 127 loop
        din <= std_logic_vector(i);
        wait for 1 ns; -- 模拟上升沿
        assert dout_s2p = expected_dout_p2s report "Error at position " & integer'image(i) severity error;
    end loop;

    -- 验证所有数据传输后，空闲标志应为高
    wait until rising_edge(clk) and empty_out = '1';
    wait;
end TB;