用VHDL实现设计并实现4*4键盘扫描控制电路，判断哪个按键被按下，在数码管上显示键值，并通过蜂鸣器发出按键音。要求: 1.键值采用16进制编码，即 16个按键分别对应显示16进制数0~F，按键 对应关系如下:最上面一行从左至右依次为0~3，第二行从左至右依次为4~7,第三行从左至右依次为8~B，最下面一行从左至右依次为C~F，其中b、d显示为小写，其他字母大写: 2.按键按下时显示当前键值并保持，直到下一按键被按下时更新显示: 3.当按键被按下时蜂鸣器发出按键音(中音3)，放开后蜂鸣器不发声; 4.选做:每个按键对应不同的按键音。

这是一个非常具体的设计实现问题，需要进行详细的硬件电路设计和程序编写。以下是一个基本的设计思路：

1. 硬件设计

使用4*4矩阵键盘，将其连接到FPGA上，通过VHDL代码实现扫描控制电路。具体实现方法如下：

1）将键盘的4行和4列分别接到FPGA的4个输入引脚和4个输出引脚上；

2）FPGA通过输出引脚依次扫描每一列，然后通过输入引脚读取每一行的状态；

3）通过判断当前按下的按键位置，将其对应的16进制数值存储在FPGA内部寄存器中；

4）通过FPGA内部的数字转换电路，将16进制数值转换为数码管上的显示值，并将其输出到数码管上；

5）同时，通过FPGA内部的蜂鸣器控制电路，控制蜂鸣器的开关，从而实现按键音的发声和停止。

2. VHDL代码编写

具体的VHDL代码实现过程需要根据实际情况进行设计，以下是一种可能的实现思路：

1）定义输入输出端口：

entity keyboard is
    port (
        ROW: in std_logic_vector(3 downto 0);
        COL: out std_logic_vector(3 downto 0);
        KEY: out std_logic_vector(3 downto 0)
    );
end entity keyboard;

entity display is
    port (
        HEX: out std_logic_vector(6 downto 0);
        SEG: out std_logic_vector(6 downto 0)
    );
end entity display;

entity buzzer is
    port (
        SOUND: out std_logic
    );
end entity buzzer;

2）定义内部信号：

architecture rtl of keyboard is
    signal row_sel: std_logic_vector(3 downto 0);
    signal col_sel: std_logic_vector(3 downto 0);
    signal key_val: std_logic_vector(3 downto 0);
    signal key_press: std_logic;
    signal key_release: std_logic;
    signal debounce: std_logic_vector(3 downto 0);
end architecture rtl;

3）实现键盘扫描控制电路：

architecture rtl of keyboard is
    begin
    -- 行列扫描控制
    row_sel <= "1110";
    col_sel <= "0111";
    COL <= col_sel;
    process(row_sel)
    begin
        KEY <= "1111";
        wait for 1 us;
        KEY <= key_val;
    end process;
    process(col_sel)
    begin
        row_sel <= "1110";
        wait for 1 us;
        if (ROW = "1110") then
            key_val <= "0111";
        elsif (ROW = "1101") then
            key_val <= "0116";
        elsif (ROW = "1011") then
            key_val <= "011B";
        elsif (ROW = "0111") then
            key_val <= "011F";
        else
            key_val <= "1111";
        end if;
        row_sel <= "1101";
        wait for 1 us;
        if (ROW = "1110") then
            key_val <= "0107";
        elsif (ROW = "1101") then
            key_val <= "010E";
        elsif (ROW = "1011") then
            key_val <= "010B";
        elsif (ROW = "0111") then
            key_val <= "010F";
        else
            key_val <= "1111";
        end if;
        row_sel <= "1011";
        wait for 1 us;
        if (ROW = "1110") then
            key_val <= "0087";
        elsif (ROW = "1101") then
            key_val <= "008E";
        elsif (ROW = "1011") then
            key_val <= "008B";
        elsif (ROW = "0111") then
            key_val <= "008F";
        else
            key_val <= "1111";
        end if;
        row_sel <= "0111";
        wait for 1 us;
        if (ROW = "1110") then
            key_val <= "00C7";
        elsif (ROW = "1101") then
            key_val <= "00CE";
        elsif (ROW = "1011") then
            key_val <= "00CB";
        elsif (ROW = "0111") then
            key_val <= "00CF";
        else
            key_val <= "1111";
        end if;
    end process;
    -- 按键消抖
    process(key_val, debounce)
    begin
        if (key_val /= "1111") then
            debounce <= debounce(2 downto 0) & '1';
            if (debounce = "1111") then
                key_press <= '1';
            end if;
        else
            debounce <= debounce(2 downto 0) & '0';
            if (debounce = "0000") then
                key_release <= '1';
            end if;
        end if;
    end process;
end architecture rtl;

4）实现数码管显示控制电路：

architecture rtl of display is
    signal hex_val: std_logic_vector(3 downto 0);
    signal seg_val: std_logic_vector(6 downto 0);
begin
    process(hex_val)
    begin
        case hex_val is
            when "0000" => seg_val <= "1111110"; -- 0
            when "0001" => seg_val <= "0110000"; -- 1
            when "0010" => seg_val <= "1101101"; -- 2
            when "0011" => seg_val <= "1111001"; -- 3
            when "0100" => seg_val <= "0110011"; -- 4
            when "0101" => seg_val <= "1011011"; -- 5
            when "0110" => seg_val <= "1011111"; -- 6
            when "0111" => seg_val <= "1110000"; -- 7
            when "1000" => seg_val <= "1111111"; -- 8
            when "1001" => seg_val <= "1110011"; -- 9
            when "1010" => seg_val <= "1110111"; -- A
            when "1011" => seg_val <= "0011111"; -- b
            when "1100" => seg_val <= "1001110"; -- C
            when "1101" => seg_val <= "0111101"; -- d
            when "1110" => seg_val <= "1001111"; -- E
            when "1111" => seg_val <= "1000111"; -- F
            when others => seg_val <= "1111111";
        end case;
    end process;
end architecture rtl;

5）实现蜂鸣器控制电路：

architecture rtl of buzzer is
    signal buzzer_on: std_logic;
begin
    process(key_press, key_release)
    begin
        if (key_press = '1') then
            buzzer_on <= '1';
        elsif (key_release = '1') then
            buzzer_on <= '0';
        end if;
    end process;
    SOUND <= buzzer_on;
end architecture rtl;

以上是一个基本的设计思路，具体实现过程需要根据实际情况进行优化和改进。