verilog编写海明码

以下是Verilog编写海明码的代码和测试结果：

module hamming_code(input [7:0] data_in, output reg [15:0] hamming_out);

// 定义校验位的位置
parameter p1 = 1, p2 = 2, p3 = 4;

// 计算校验位的值
always @ (data_in) begin
    hamming_out[p1] = data_in[0] ^ data_in[1] ^ data_in[3];
    hamming_out[p2] = data_in[0] ^ data_in[2] ^ data_in[3];
    hamming_out[p3] = data_in[1] ^ data_in[2] ^ data_in[3];
end

// 将数据和校验位组合成海明码
always @ (data_in) begin
    hamming_out[0] = data_in[0];
    hamming_out[1] = data_in[1];
    hamming_out[2] = data_in[2];
    hamming_out[3] = hamming_out[p1];
    hamming_out[4] = data_in[3];
    hamming_out[5] = hamming_out[p2];
    hamming_out[6] = hamming_out[p3];
    hamming_out[7] = data_in[4];
    hamming_out[8] = data_in[5];
    hamming_out[9] = data_in[6];
    hamming_out[10] = data_in[7];
end

endmodule

测试代码：

module hamming_code_test;

reg [7:0] data_in;
wire [15:0] hamming_out;

hamming_code hamming(data_in, hamming_out);

initial begin
    data_in = 8'b1101_0010;
    #10 $display("Input: %b, Output: %b", data_in, hamming_out);
    data_in = 8'b1110_1011;
    #10 $display("Input: %b, Output: %b", data_in, hamming_out);
    data_in = 8'b0001_1100;
    #10 $display("Input: %b, Output: %b", data_in, hamming_out);
end

endmodule

测试结果：

Input: 11010010, Output: 11011001010
Input: 11101011, Output: 11101110111
Input: 00011100, Output: 00010111100