用Verlog代码写一个Moore型状态机，要求能设计一个可以识别“01101”的序列检测电路

以下是一个可以识别“01101”的序列检测电路的Moore型状态机的Verilog代码：

module sequence_detector (
    input clk,
    input reset_n,
    input data,
    output reg detected
);

    parameter IDLE = 2'b00;
    parameter READ_0 = 2'b01;
    parameter READ_01 = 2'b10;
    parameter READ_011 = 2'b11;

    reg [1:0] state;
    
    always @(posedge clk or negedge reset_n) begin
        if (~reset_n) begin
            state <= IDLE;
            detected <= 0;
        end else begin
            case (state)
                IDLE: begin
                    if (data == 0) begin
                        state <= READ_0;
                        detected <= 0;
                    end else begin
                        state <= IDLE;
                        detected <= 0;
                    end
                end
                
                READ_0: begin
                    if (data == 1) begin
                        state <= READ_01;
                        detected <= 0;
                    end else begin
                        state <= IDLE;
                        detected <= 0;
                    end
                end
                
                READ_01: begin
                    if (data == 1) begin
                        state <= READ_01;
                        detected <= 0;
                    end else if (data == 0) begin
                        state <= READ_011;
                        detected <= 0;
                    end else begin
                        state <= IDLE;
                        detected <= 0;
                    end
                end
                
                READ_011: begin
                    if (data == 0) begin
                        state <= READ_0;
                        detected <= 0;
                    end else if (data == 1) begin
                        state <= READ_01;
                        detected <= 0;
                    end else if (data == 1) begin
                        state <= READ_011;
                        detected <= 1;
                    end else begin
                        state <= IDLE;
                        detected <= 0;
                    end
                end
                
                default: begin
                    state <= IDLE;
                    detected <= 0;
                end
            endcase
        end
    end
    
endmodule

该状态机有四个状态：IDLE、READ_0、READ_01和READ_011。当输入序列为“01101”时，该状态机会检测到并将输出detected设置为1。注意，在每个状态下，如果输入不符合预期，状态机都会返回到IDLE状态，并将输出detected设置为0。