设计序列检测器连续检测串行二进制码，只要出现连续的“101”，即输出 1，否则输出 0。写出该序列检测器的摩尔型状态机VERILOG 代码，给出完整代码，并尽量不报错

设计一个简单的Moore型状态机（Verilog代码）用于检测连续的"101"序列，我们可以使用有限状态机（FSM）。以下是一个基本的Verilog代码示例：

module binary_sequence_detector (
    input [2:0] bin_input,   // 3位输入，假设代表二进制数据
    output reg detected,      // 输出信号，0 或 1
    input reset                // 重置输入
);

// 定义状态变量和转换条件
typedef enum {IDLE, COUNT_1, COUNT_2, DETECTED, NOT_DETECTED} State;

State state;
reg [1:0] count;       // 计数寄存器

// 状态机转换函数
always @(posedge bin_input or posedge reset) begin
    if (reset) begin
        state <= IDLE;
        count <= 0;
    end else begin
        case(state)
            IDLE: begin
                if (bin_input == 3'b101) begin
                    state <= COUNT_1;
                    count <= 1;
                end else begin
                    state <= NOT_DETECTED;
                end
            end
            COUNT_1: begin
                if (bin_input == 3'b0) begin
                    state <= COUNT_2;
                    count <= 2;
                end else begin
                    state <= NOT_DETECTED;
                    count <= 0;
                end
            end
            COUNT_2: begin
                if (bin_input == 3'b0) begin
                    state <= DETECTED;
                    detected <= 1;
                end else begin
                    state <= NOT_DETECTED;
                    count <= 0;
                end
            end
            default: begin
                state <= NOT_DETECTED;
                count <= 0;
            end
        endcase
    end
end

endmodule