modelsim设计双端口寄存器堆设计

下面是使用 ModelSim 设计双端口寄存器堆的一个例子：

1. 创建一个新的 VHDL 文件，命名为 dual_port_ram.vhd。在文件中定义双端口寄存器堆的实体和端口：

entity dual_port_ram is
    generic (
        WIDTH   : integer := 32;
        DEPTH   : integer := 64
    );
    port (
        clk1        : in    std_logic;
        clk2        : in    std_logic;
        we1         : in    std_logic;
        we2         : in    std_logic;
        addr1       : in    integer range 0 to DEPTH-1;
        addr2       : in    integer range 0 to DEPTH-1;
        din1        : in    std_logic_vector(WIDTH-1 downto 0);
        din2        : in    std_logic_vector(WIDTH-1 downto 0);
        dout1       : out   std_logic_vector(WIDTH-1 downto 0);
        dout2       : out   std_logic_vector(WIDTH-1 downto 0)
    );
end entity dual_port_ram;

2. 在文件中定义双端口寄存器堆的行为。可以使用 RAM 或者 D 触发器来实现双端口寄存器堆。这里使用 RAM 实现：

architecture ram_arch of dual_port_ram is
    type ram_type is array (0 to DEPTH-1) of std_logic_vector(WIDTH-1 downto 0);
    signal ram : ram_type := (others => (others => '0'));
begin
    process (clk1, clk2)
    begin
        if rising_edge(clk1) then
            if we1 = '1' then
                ram(addr1) <= din1;
            end if;
            dout1 <= ram(addr1);
        end if;
        if rising_edge(clk2) then
            if we2 = '1' then
                ram(addr2) <= din2;
            end if;
            dout2 <= ram(addr2);
        end if;
    end process;
end architecture ram_arch;

3. 编译并运行仿真。可以使用 ModelSim 自带的波形编辑器来验证设计的正确性：

library ieee;
use ieee.std_logic_1164.all;
use work.dual_port_ram.all;

entity dual_port_ram_tb is
end entity dual_port_ram_tb;

architecture tb_arch of dual_port_ram_tb is
    component dual_port_ram is
        generic (
            WIDTH   : integer := 32;
            DEPTH   : integer := 64
        );
        port (
            clk1        : in    std_logic;
            clk2        : in    std_logic;
            we1         : in    std_logic;
            we2         : in    std_logic;
            addr1       : in    integer range 0 to DEPTH-1;
            addr2       : in    integer range 0 to DEPTH-1;
            din1        : in    std_logic_vector(WIDTH-1 downto 0);
            din2        : in    std_logic_vector(WIDTH-1 downto 0);
            dout1       : out   std_logic_vector(WIDTH-1 downto 0);
            dout2       : out   std_logic_vector(WIDTH-1 downto 0)
        );
    end component dual_port_ram;
    
    signal clk1        : std_logic := '0';
    signal clk2        : std_logic := '0';
    signal we1         : std_logic := '0';
    signal we2         : std_logic := '0';
    signal addr1       : integer range 0 to 63 := 0;
    signal addr2       : integer range 0 to 63 := 0;
    signal din1        : std_logic_vector(31 downto 0) := (others => '0');
    signal din2        : std_logic_vector(31 downto 0) := (others => '0');
    signal dout1       : std_logic_vector(31 downto 0) := (others => '0');
    signal dout2       : std_logic_vector(31 downto 0) := (others => '0');
begin
    dut : dual_port_ram generic map(
        WIDTH   => 32,
        DEPTH   => 64
    ) port map (
        clk1    => clk1,
        clk2    => clk2,
        we1     => we1,
        we2     => we2,
        addr1   => addr1,
        addr2   => addr2,
        din1    => din1,
        din2    => din2,
        dout1   => dout1,
        dout2   => dout2
    );
    
    clk1_process : process
    begin
        clk1 <= '0';
        wait for 10 ns;
        clk1 <= '1';
        wait for 10 ns;
    end process clk1_process;

    clk2_process : process
    begin
        clk2 <= '0';
        wait for 20 ns;
        clk2 <= '1';
        wait for 20 ns;
    end process clk2_process;

    stim_process : process
    begin
        we1 <= '1';
        we2 <= '1';
        din1 <= "00000000000000000000000000000001";
        din2 <= "00000000000000000000000000000010";
        addr1 <= 0;
        addr2 <= 1;
        wait for 20 ns;
        we1 <= '0';
        we2 <= '0';
        addr1 <= 0;
        addr2 <= 1;
        wait for 20 ns;
        we1 <= '1';
        we2 <= '1';
        din1 <= "00000000000000000000000000000010";
        din2 <= "00000000000000000000000000000001";
        addr1 <= 1;
        addr2 <= 0;
        wait for 20 ns;
        we1 <= '0';
        we2 <= '0';
        addr1 <= 1;
        addr2 <= 0;
        wait for 20 ns;
        wait;
    end process stim_process;
end architecture tb_arch;

运行仿真后，可以在波形编辑器中观察到读写操作的正确性。