set input delay
时间: 2023-09-26 17:11:59 浏览: 56
set_input_delay是一个I/O Delay约束命令,用于设置输入信号相对于时钟边沿的延迟。该命令可以通过设置一个正或负的延迟值(单位为ns)来控制输入信号的到达时间。这个命令可以在FPGA设计中使用,以确保正确的数据采样和时序关系。引用<span class="em">1</span><span class="em">2</span><span class="em">3</span>
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- *1* *2* [set_input_delay如何使用?](https://blog.csdn.net/zhanghaijun2013/article/details/126733616)[target="_blank" data-report-click={"spm":"1018.2226.3001.9630","extra":{"utm_source":"vip_chatgpt_common_search_pc_result","utm_medium":"distribute.pc_search_result.none-task-cask-2~all~insert_cask~default-1-null.142^v93^chatsearchT3_1"}}] [.reference_item style="max-width: 50%"]
- *3* [VIVADO时序约束之Input Delay(set_input_delay)](https://blog.csdn.net/aaaaaaaa585/article/details/118859268)[target="_blank" data-report-click={"spm":"1018.2226.3001.9630","extra":{"utm_source":"vip_chatgpt_common_search_pc_result","utm_medium":"distribute.pc_search_result.none-task-cask-2~all~insert_cask~default-1-null.142^v93^chatsearchT3_1"}}] [.reference_item style="max-width: 50%"]
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