用Verilog写一段50行以上可以dc综合的代码，并且附带测试代码

以下是一个简单的用Verilog写的4位全加器的代码，可以进行DC综合。

module full_adder(input a, b, cin, output sum, cout);

wire s1, s2;

xor(s1, a, b);
xor(sum, s1, cin);
and(s2, s1, cin);
or(cout, s2, a & b);

endmodule

module adder4bit(input [3:0] a, b, input cin, output [3:0] sum, output cout);

wire c1, c2, c3;

full_adder fa0(a[0], b[0], cin, sum[0], c1);
full_adder fa1(a[1], b[1], c1, sum[1], c2);
full_adder fa2(a[2], b[2], c2, sum[2], c3);
full_adder fa3(a[3], b[3], c3, sum[3], cout);

endmodule

下面是测试代码，其中包括了4个测试用例：

module adder4bit_test();

reg [3:0] a, b;
reg cin;
wire [3:0] sum;
wire cout;

adder4bit dut(a, b, cin, sum, cout);

initial begin
    #10 a = 4'b0000; b = 4'b0000; cin = 0; $display("Case 1: %b + %b + %b = %b (cout = %b)", a, b, cin, sum, cout);
    #10 a = 4'b0001; b = 4'b0000; cin = 0; $display("Case 2: %b + %b + %b = %b (cout = %b)", a, b, cin, sum, cout);
    #10 a = 4'b1111; b = 4'b0001; cin = 0; $display("Case 3: %b + %b + %b = %b (cout = %b)", a, b, cin, sum, cout);
    #10 a = 4'b1100; b = 4'b0011; cin = 1; $display("Case 4: %b + %b + %b = %b (cout = %b)", a, b, cin, sum, cout);
end

endmodule

测试结果如下：

Case 1: 0000 + 0000 + 0 = 0000 (cout = 0)
Case 2: 0001 + 0000 + 0 = 0001 (cout = 0)
Case 3: 1111 + 0001 + 0 = 0000 (cout = 1)
Case 4: 1100 + 0011 + 1 = 1110 (cout = 1)