uart带fifo,接收,控制,发送的verilog代码及其测试代码

以下是一个简单的UART带FIFO的Verilog代码，包含接收、控制和发送模块，同时也包含了测试代码进行验证。

module uart_fifo(
    input clk, // 时钟信号
    input rst, // 复位信号

    input rx, // 接收端口
    output tx, // 发送端口

    input [7:0] data_in, // 发送数据输入
    input send_en, // 发送使能信号

    output [7:0] data_out, // 接收数据输出
    output recv_en, // 接收使能信号
    output full, // FIFO满标志位
    output empty // FIFO空标志位
);

// 定义FIFO深度
parameter DEPTH = 16;

// 定义状态机状态
localparam IDLE = 2'b00;
localparam RECV = 2'b01;
localparam SEND = 2'b10;

// 定义状态机信号
reg [1:0] state_reg, state_next;
reg [3:0] cnt_reg, cnt_next;

// 定义FIFO信号
reg [7:0] fifo[DEPTH-1:0];
reg [3:0] head_reg, head_next;
reg [3:0] tail_reg, tail_next;
wire [3:0] count;

// 定义接收端口信号
reg rx_reg, rx_next;

// 定义发送端口信号
reg tx_reg, tx_next;

// 定义发送数据信号
reg [7:0] data_reg;

// 定义状态机
always @ (posedge clk or posedge rst) begin
    if (rst) begin
        state_reg <= IDLE;
        cnt_reg <= 0;
        head_reg <= 0;
        tail_reg <= 0;
        rx_reg <= 1;
        tx_reg <= 1;
        data_reg <= 0;
    end else begin
        state_reg <= state_next;
        cnt_reg <= cnt_next;
        head_reg <= head_next;
        tail_reg <= tail_next;
        rx_reg <= rx_next;
        tx_reg <= tx_next;
        data_reg <= data_in;
    end
end

// 定义发送模块
always @ (posedge clk or posedge rst) begin
    if (rst) begin
        tx_next <= 1;
    end else begin
        case (state_reg)
            IDLE: begin
                if (send_en) begin
                    tx_next <= 0;
                    state_next <= SEND;
                    cnt_next <= 0;
                end else begin
                    tx_next <= 1;
                    state_next <= IDLE;
                    cnt_next <= 0;
                end
            end

            SEND: begin
                if (cnt_reg < 10) begin // 发送前导位
                    tx_next <= 0;
                    state_next <= SEND;
                    cnt_next <= cnt_reg + 1;
                end else if (cnt_reg == 10) begin // 发送起始位
                    tx_next <= 0;
                    state_next <= SEND;
                    cnt_next <= cnt_reg + 1;
                end else if (cnt_reg < 18) begin // 发送数据位
                    tx_next <= data_reg[cnt_reg-11];
                    state_next <= SEND;
                    cnt_next <= cnt_reg + 1;
                end else if (cnt_reg == 18) begin // 发送停止位
                    tx_next <= 1;
                    state_next <= IDLE;
                    cnt_next <= 0;
                end
            end
        endcase
    end
end

// 定义接收模块
always @ (posedge clk or posedge rst) begin
    if (rst) begin
        rx_next <= 1;
        count <= 0;
    end else begin
        case (state_reg)
            IDLE: begin
                rx_next <= rx;
                state_next <= RECV;
            end

            RECV: begin
                if (cnt_reg < 8) begin // 接收数据位
                    fifo[tail_reg] <= {fifo[tail_reg][6:0], rx_reg};
                    cnt_next <= cnt_reg + 1;
                    tail_next <= (tail_reg == DEPTH-1) ? 0 : tail_reg + 1;
                    rx_next <= rx;
                    state_next <= RECV;
                end else if (cnt_reg == 8) begin // 接收停止位
                    cnt_next <= 0;
                    rx_next <= rx;
                    state_next <= IDLE;
                end
            end
        endcase
    end
end

// 定义FIFO
assign count = (head_reg <= tail_reg) ? tail_reg - head_reg : DEPTH - head_reg + tail_reg;
assign full = (count == DEPTH-1);
assign empty = (count == 0);

// 定义发送数据输出
assign data_out = fifo[head_reg];

// 定义接收使能信号
assign recv_en = ~full;

// 定义状态机状态转换
always @ (*) begin
    case (state_reg)
        IDLE: begin
            if (~rx_reg & rx_next) begin
                state_next = RECV;
            end else if (send_en) begin
                state_next = SEND;
            end else begin
                state_next = IDLE;
            end
        end

        RECV: begin
            if (cnt_reg == 8) begin
                state_next = IDLE;
            end else begin
                state_next = RECV;
            end
        end

        SEND: begin
            if (cnt_reg == 18) begin
                state_next = IDLE;
            end else begin
                state_next = SEND;
            end
        end
    endcase
end

// 定义FIFO读写指针更新
always @ (*) begin
    if (state_reg == RECV & ~full) begin
        head_next = (head_reg == DEPTH-1) ? 0 : head_reg + 1;
    end
end

// 定义测试代码
initial begin
    $dumpfile("uart_fifo.vcd");
    $dumpvars(0, uart_fifo);

    // 发送3个字节
    data_in <= 8'h41;
    send_en <= 1;
    #10;
    send_en <= 0;
    #10;

    data_in <= 8'h42;
    send_en <= 1;
    #10;
    send_en <= 0;
    #10;

    data_in <= 8'h43;
    send_en <= 1;
    #10;
    send_en <= 0;
    #10;

    // 接收3个字节
    rx <= 0;
    #10;

    rx <= 1;
    #10;

    rx <= 0;
    #10;

    rx <= 1;
    #10;

    rx <= 0;
    #10;

    rx <= 1;
    #10;

    $finish;
end

endmodule

测试代码中，首先发送3个字节，然后通过模拟发送端口和接收端口的信号进行接收，最后停止仿真。可以通过仿真波形验证UART模块的正确性。