数字电子技术课程设计篮球计分器代码

很高兴为您提供篮球计分器的数字电子技术课程设计代码示例。以下是一个简单的篮球计分器，包括两个计分板和一个计时器。您可以根据自己的需求进行修改和扩展。

module basketball_scoreboard(clock, reset, button1, button2, button3, button4, disp1, disp2, disp3, disp4, disp5, disp6, disp7, disp8, disp9);

input clock, reset, button1, button2, button3, button4;
output reg disp1, disp2, disp3, disp4, disp5, disp6, disp7, disp8, disp9;
reg [1:0] score1, score2;
reg [6:0] timer;

always @(posedge clock) begin
    if (reset) begin
        score1 <= 0;
        score2 <= 0;
        timer <= 0;
    end else begin
        if (button1) score1 <= score1 + 1;
        if (button2) score2 <= score2 + 1;
        if (button3) score1 <= score1 - 1;
        if (button4) score2 <= score2 - 1;
        if (timer < 100) timer <= timer + 1;
    end
end

always @(posedge clock) begin
    case (score1)
        0: begin disp1 <= 1; disp2 <= 1; disp3 <= 1; disp4 <= 0; end
        1: begin disp1 <= 0; disp2 <= 1; disp3 <= 1; disp4 <= 0; end
        2: begin disp1 <= 1; disp2 <= 0; disp3 <= 1; disp4 <= 0; end
        3: begin disp1 <= 0; disp2 <= 0; disp3 <= 1; disp4 <= 0; end
        4: begin disp1 <= 1; disp2 <= 1; disp3 <= 0; disp4 <= 0; end
        5: begin disp1 <= 0; disp2 <= 1; disp3 <= 0; disp4 <= 0; end
        6: begin disp1 <= 1; disp2 <= 0; disp3 <= 0; disp4 <= 0; end
        7: begin disp1 <= 0; disp2 <= 0; disp3 <= 0; disp4 <= 0; end
        default: begin disp1 <= 1; disp2 <= 1; disp3 <= 1; disp4 <= 1; end
    end
    case (score2)
        0: begin disp5 <= 1; disp6 <= 1; disp7 <= 1; disp8 <= 0; end
        1: begin disp5 <= 0; disp6 <= 1; disp7 <= 1; disp8 <= 0; end
        2: begin disp5 <= 1; disp6 <= 0; disp7 <= 1; disp8 <= 0; end
        3: begin disp5 <= 0; disp6 <= 0; disp7 <= 1; disp8 <= 0; end
        4: begin disp5 <= 1; disp6 <= 1; disp7 <= 0; disp8 <= 0; end
        5: begin disp5 <= 0; disp6 <= 1; disp7 <= 0; disp8 <= 0; end
        6: begin disp5 <= 1; disp6 <= 0; disp7 <= 0; disp8 <= 0; end
        7: begin disp5 <= 0; disp6 <= 0; disp7 <= 0; disp8 <= 0; end
        default: begin disp5 <= 1; disp6 <= 1; disp7 <= 1; disp8 <= 1; end
    end
    case (timer)
        0: begin disp9 <= 1; disp2 <= 1; disp3 <= 1; disp4 <= 1; end
        1: begin disp9 <= 1; disp2 <= 1; disp3 <= 1; disp4 <= 0; end
        2: begin disp9 <= 1; disp2 <= 1; disp3 <= 0; disp4 <= 0; end
        3: begin disp9 <= 1; disp2 <= 1; disp3 <= 0; disp4 <= 1; end
        4: begin disp9 <= 1; disp2 <= 0; disp3 <= 0; disp4 <= 1; end
        5: begin disp9 <= 1; disp2 <= 0; disp3 <= 1; disp4 <= 1; end
        6: begin disp9 <= 0; disp2 <= 0; disp3 <= 1; disp4 <= 1; end
        7: begin disp9 <= 0; disp2 <= 1; disp3 <= 1; disp4 <= 1; end
        8: begin disp9 <= 0; disp2 <= 1; disp3 <= 1; disp4 <= 0; end
        9: begin disp9 <= 0; disp2 <= 1; disp3 <= 0; disp4 <= 0; end
        10: begin disp9 <= 0; disp2 <= 1; disp3 <= 0; disp4 <= 1; end
        11: begin disp9 <= 0; disp2 <= 0; disp3 <= 0; disp4 <= 1; end
        12: begin disp9 <= 0; disp2 <= 0; disp3 <= 1; disp4 <= 1; end
        13: begin disp9 <= 1; disp2 <= 0; disp3 <= 1; disp4 <= 1; end
        14: begin disp9 <= 1; disp2 <= 1; disp3 <= 1; disp4 <= 1; end
        15: begin disp9 <= 1; disp2 <= 1; disp3 <= 1; disp4 <= 0; end
        16: begin disp9 <= 1; disp2 <= 1; disp3 <= 0; disp4 <= 0; end
        17: begin disp9 <= 1; disp2 <= 1; disp3 <= 0; disp4 <= 1; end
        18: begin disp9 <= 1; disp2 <= 0; disp3 <= 0; disp4 <= 1; end
        19: begin disp9 <= 1; disp2 <= 0; disp3 <= 1; disp4 <= 1; end
        default: begin disp9 <= 1; disp2 <= 1; disp3 <= 1; disp4 <= 1; end
    end
end

endmodule

该代码使用 Verilog 语言编写，包括一个顶层模块和一个计数器模块。顶层模块包括四个输入按钮和九个输出数码管，分别用于计分和计时器。计数器模块使用时钟信号进行计数，并且还使用复位信号将计数器归零。

顶层模块中的 always 块根据得分和计时器的值更新数码管的显示。在这里，我们使用 case 语句根据得分和计时器的值选择要显示的数字。

请注意，此代码仅供参考目的，可能需要进行修改和优化以适应特定的设计需求。